Display Panel Common Electrode Auxiliary Patterns and Staggered Spacers

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Solution Overview

Problem

Conventional FFS display panels face issues with uneven brightness due to high resistance of the common electrode, leading to spacer misalignment under external forces, affecting display reliability.

Innovation Solution

A display panel design featuring a common electrode layer with auxiliary conductive patterns connected to it, where spacers are staggered with respect to these patterns to prevent overlap and ensure stability, thereby maintaining display reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a metal pattern is added to the planar common electrode to reduce resistance, then the resistance is reduced and brightness uniformity is improved, but a level difference is created between areas with and without the metal pattern

Engineering Contradiction:
Improvebrightness uniformityVSAvoidsurface flatness
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

The patent applies local quality by making the common electrode layer have different properties in different areas. Specifically, the common electrode layer is designed with a first region (under the metal pattern) and a second region (without metal pattern), where the first region has different thickness or structural characteristics to compensate for the level difference caused by the metal pattern addition. This local variation ensures that both regions maintain similar electrical conductivity while preserving surface flatness.

Inventive Principle:
Principle #3Local quality

2Reliability

If a metal pattern is added to reduce common electrode resistance, then electrical conductivity is improved, but spacers become prone to shifting and misalignment under external force

Engineering Contradiction:
Improveelectrical conductivityVSAvoidspacer position stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies preliminary action by pre-compensating for the potential level difference through the design of the common electrode layer structure before the metal pattern is added. The common electrode layer is configured with specific thickness variations or structural features in advance, so that when the metal pattern is subsequently added, no significant level difference occurs, thereby preventing spacer misalignment from the outset.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the common electrode resistance is reduced by adding metal pattern, then voltage distribution uniformity is improved, but the panel structure becomes more complex

Engineering Contradiction:
Improvevoltage distribution uniformityVSAvoidelectrode structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies merging by integrating the common electrode layer and the metal pattern into a unified, closely coupled structure. The metal pattern is directly formed on or integrated with the common electrode layer, creating a combined electrical structure that functions as a single entity. This integration simplifies the overall design compared to separate components, while achieving improved voltage distribution uniformity through the synergistic effect of the layered construction.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12066723B2Display panel and display device
Publication Date: 2024.08.20 TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD
  • US12066723B2 patent drawing
  • US12066723B2 patent drawing
  • US12066723B2 patent drawing

AI summary

The present application provides a display panel and a display device. The display panel includes: thin film transistors arranged on the first substrate; a common electrode layer arranged on the thin film transistors; auxiliary conductive patterns disposed on the common electrode layer and connected to the common electrode layer; a pixel electrode layer electrically insulated from the common electrode layer and the auxiliary conductive patterns; and spacers arranged between the first substrate and the second substrate and staggered with respect to the auxiliary conductive patterns.