Display Panel Conductive Layer Varying Line Widths
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Solution Overview
Problem
The manufacturing of display panels with liquid crystal displays faces challenges in achieving reliable conductive layers with sufficient line widths and controlling parasitic capacitance, leading to issues with yield and electrical performance due to over-etching and faulty design.
Innovation Solution
The design incorporates a conductive layer with varying line widths at different heights, ensuring sufficient line widths post-patterning and controlling parasitic capacitance by adjusting line widths at overlapping and non-overlapping positions, thereby preventing over-etching and enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the conductive layer has a uniform line width throughout, then the manufacturing process is simpler, but the conductive layer is prone to over-etching and breakage during patterning
Solution Approach 1:
The conductive layer is designed with different line widths at different locations: a first line width in the overlapping region and a second line width in the non-overlapping region. This local differentiation allows the overlapping region to have sufficient width for etching margin while the non-overlapping region maintains appropriate capacitance levels, thereby preventing both over-etching breakage and excessive parasitic capacitance.
2Reliability
If the conductive layer line width is increased to prevent breakage, then the reliability improves, but the parasitic capacitance between overlapping conductive layers increases
Solution Approach 1:
The patent applies different line widths to different functional regions of the conductive layer. The overlapping region uses a first line width that provides sufficient mechanical strength and etching margin to prevent breakage, while the non-overlapping region uses a second line width that minimizes parasitic capacitance. This localized differentiation resolves the contradiction between reliability and parasitic capacitance control.
3Object-generated harmful factors
If the conductive layer line width is decreased to reduce parasitic capacitance, then the electrical performance improves, but the conductive layer becomes susceptible to over-etching and breakage
Solution Approach 1:
The conductive layer is designed with spatially varying line widths where the overlapping region maintains a larger first line width to ensure structural integrity and resistance to over-etching, while the non-overlapping region uses a smaller second line width to reduce parasitic capacitance. This local differentiation allows each region to optimize for its specific functional requirement.
Data Source
AI summary
A display panel comprises a first substrate, a second substrate opposite to the first substrate, and a display medium layer disposed between the first and second substrates. The first substrate comprises a conductive layer formed on the first base plate and extending along a first direction. Along the first direction, the conductive layer comprises a first plane correspondingly at a first height, a tilted plane, and a second plane correspondingly at a second height in sequential order. The first height is greater than the second height. A position of the first plane adjacent to the tilted plane of the conductive layer has a first line width along the second direction. A position of the tilted plane adjacent to the second plane of the conductive layer has a second line width along the second direction. The first line width is shorter than the second line width.