Display Panel Control Transistors for Voltage Signal Consistency

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Solution Overview

Problem

In display panels, different connection traces have varying loads due to different overlapping areas with a power bus, leading to inconsistent voltage signals transmitted to data lines, causing display non-uniformity and affecting product evaluation during screen lighting tests.

Innovation Solution

The display panel design includes a control circuit with control transistors having different channel areas and overlapping areas with a power bus, which compensates for load differences by adjusting parasitic capacitances to ensure consistent voltage signals across data lines, thereby improving signal homogeneity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If connection traces have different overlapping areas with the power bus, then the layout flexibility and space utilization are improved, but the voltage signal consistency deteriorates due to varying parasitic capacitances

Engineering Contradiction:
Improveoverlapping area with power busVSAvoidvoltage signal consistency
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent applies local quality by configuring different channel areas for control transistors based on their specific positions and overlapping areas with the power bus. Connection traces with larger overlapping areas (higher parasitic capacitance) are paired with control transistors having larger channel areas, while those with smaller overlapping areas are paired with control transistors having smaller channel areas. This localized adaptation ensures that each connection trace-group transistor pair operates with matched characteristics, maintaining voltage signal consistency despite varying overlapping areas.

Inventive Principle:
Principle #3Local quality

2Reliability

If control transistors have different channel areas, then the voltage signal consistency is improved by compensating for parasitic capacitance differences, but the manufacturing complexity increases

Engineering Contradiction:
Improvevoltage signal consistencyVSAvoidcontrol transistor configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements parameter changes by systematically varying the channel areas of control transistors to match the parasitic capacitance characteristics of different connection traces. This parameter adaptation allows the circuit to compensate for the varying overlapping areas with the power bus, ensuring consistent voltage signals are transmitted to all data lines despite the structural variations in the connection traces.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the consistency of voltage signals transmitted to data lines, reducing display non-uniformity and improving the reliability of product evaluations by compensating for load-induced signal variations.

Implementation Method 1

Each of the connection traces at least partially overlaps with the power bus in a directions perpendicular to a plane of the display panel, and has a first area that is an overlapping area between the connection trace and the power bus. The first area of one of the connection traces that is coupled to the first control transistor is different from the first area of another one of the connection traces that is coupled to the second control transistor.

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS11763734B2Display panel and display apparatus
Publication Date: 2023.09.19 WUHAN TIANMA MICRO ELECTRONICS CO LTD
  • US11763734B2 patent drawing
  • US11763734B2 patent drawing
  • US11763734B2 patent drawing

AI summary

A display panel and a display apparatus are provided. The display panel includes data lines located in a display region, and a power bus, connection traces, and a control circuit that are located in a non-display region. The connection trace at least partially overlaps with the power bus in a direction perpendicular to a plane of the display panel, and has a first area that is an overlapping area between the connection trace and the power bus. The control circuit includes control transistors. A first electrode and/or a second electrode of the control transistor is coupled to the connection trace. The control transistors include a first control transistor and a second control transistor. The connection trace coupled to the first control transistor and the connection trace coupled to the second control transistor have different first areas. Channel areas of the first control transistor and the second control transistor are different.