Display Panel Cross-Coupled Gate Lines Data Line Reduction
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Solution Overview
Problem
Conventional liquid crystal display apparatuses face challenges in achieving high display quality with a reduced number of data lines, which affects image reliability and efficiency in driving gate lines without excessive design changes.
Innovation Solution
The display panel is designed with a matrix arrangement of pixels, where data lines extend parallel to the short side of each pixel, allowing sharing between adjacent pixels, and gate lines extend parallel to the long side, with a cross-coupled terminal structure to efficiently drive gate lines, reducing the number of data lines and enabling flexible driving orders without significant design modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of data lines is reduced, then display quality is improved, but image reliability deteriorates
Solution Approach 1:
Multiple gate lines (e.g., gate lines 1 and 2) are merged to share a single data line. The data line is configured to simultaneously supply data signals to multiple gate lines, reducing the total number of data lines while maintaining display functionality and reliability
2Device complexity
If the number of data lines is reduced, then device complexity is reduced, but ease of operation deteriorates
Solution Approach 1:
The gate driver is designed with dynamic control capability to independently control the timing and sequence of multiple gate lines that share data lines. This dynamic control allows flexible driving orders and maintains ease of operation despite reduced data line count
Solution Approach 2:
The gate lines are segmented into groups that share common data lines. Each gate line can be controlled independently through the gate driver, allowing flexible segmentation and reconfiguration of driving sequences without increasing overall system complexity
Data Source
AI summary
A display panel includes a plurality of pixels, data lines, gate lines, a gate driver and terminals. The plurality of pixels form a plurality of rows and columns. The plurality of data lines extend in a first direction parallel to the pixel columns. Each data line is connected to at least two adjacent pixels included in a single pixel row. The plurality of gate lines extend in a second direction parallel with the plurality of pixel rows. The gate lines each connect to at least one pixel included in a single pixel row. At least two gate lines are disposed between two adjacent pixel rows. The gate driver generates signals to drive the plurality of gate lines. The plurality of terminals receives the gate signals to transmit the gate signals to the plurality of gate lines. Some of the terminals connect with some gate lines having a cross-coupled structure.