Display Panel Data Driver Timing Compensation

Solution Overview

Problem

As the size of display panels increases, gate signals applied to areas far from the gate driver are delayed, leading to potential delays in charging data voltages to pixels, resulting in inadequate display performance.

Innovation Solution

A display apparatus with a first gate driver and a data driver that includes positive and negative amplifiers, where the driving timing of the amplifiers is independently controlled, with specific clock signals and multiphase clock signals applied to compensate for the delay in gate signals, ensuring timely data voltage delivery to pixels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the size of the display panel is increased, then the display area is enlarged, but the gate signal propagation delay increases

Engineering Contradiction:

Improvedisplay areaVSAvoidgate signal propagation delay

Core Design Contradiction:

Area of stationary objectVSLoss of time

Solution Approach 1:

The display panel is divided into multiple areas (first area and second area) with different gate signal delay characteristics. Each area is driven by corresponding amplifiers (first positive/negative amplifiers and second positive/negative amplifiers) that are independently controlled with different clock signal periods, allowing tailored compensation for each segment's specific delay.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the display panel are assigned different driving parameters. The first area uses clock signals with one period while the second area uses clock signals with a different period, matching the local delay characteristics of each region to optimize data voltage charging timing throughout the entire panel.

Inventive Principle:

Principle #3Local quality

2Loss of time

If the gate signal is delayed in distant areas, then the data voltage charging time is insufficient, but increasing the clock signal period extends the charging window

Engineering Contradiction:

Improvedata voltage charging timeVSAvoidrefresh rate

Core Design Contradiction:

Loss of timeVSProductivity

Solution Approach 1:

The display panel is divided into multiple areas (first area and second area) with different gate signal delay characteristics. Each area is driven by corresponding amplifiers (first positive/negative amplifiers and second positive/negative amplifiers) that are independently controlled with different clock signal periods, allowing tailored compensation for each segment's specific delay.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the display panel are assigned different driving parameters. The first area uses clock signals with one period while the second area uses clock signals with a different period, matching the local delay characteristics of each region to optimize data voltage charging timing throughout the entire panel.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10885823B2Display apparatus and a method of driving a display panel using the same

Publication Date: 2021.01.05 SAMSUNG DISPLAY CO LTD

AI summary

A display apparatus includes a display panel, a gate driver and a data driver. The display panel is configured to display an image. The gate driver is configured to output gate signals to the display panel. The data driver includes positive amplifiers configured to output positive data voltages to the display panel and negative amplifiers configured to output negative data voltages to the display panel. A driving timing of the positive amplifiers and a driving timing of the negative amplifiers are independently controlled.