Display Panel Drive Circuit for Low-Resolution Source Replication
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Solution Overview
Problem
The existing display panel drive circuits are in one-to-one correspondence with the display screen resolution, leading to high costs when using low-resolution signal sources to drive high-resolution panels, as seen in the excessive cost of 8K Tcon boards compared to 4K boards.
Innovation Solution
A display panel drive circuit architecture that includes a shift register, data buffer with cache units, and control circuits to multiplex and copy display data across repeat units, allowing low-resolution signal sources to drive high-resolution panels by replicating data through cache units and timing sequence control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the drive circuit resolution is in one-to-one correspondence with the display screen resolution, then the display quality is ensured, but the cost of signal source and drive board increases significantly
Solution Approach 1:
The drive circuit is divided into multiple cache units organized in repeat units, where each cache unit can independently store and output display data. This segmentation allows the system to process and replicate data from low-resolution sources to achieve high-resolution output without requiring the signal source to match the panel resolution.
Solution Approach 2:
The patent implements a data copying mechanism where display data from cache units in one repeat unit is copied to corresponding cache units in another repeat unit through control circuits. This copying function enables low-resolution data to be replicated and expanded to fill high-resolution display panels, reducing the cost of signal sources and drive boards.
2Device complexity
If multiple cache units are multiplexed with the same clock signal terminal, then the circuit complexity is reduced, but the timing control becomes more challenging
Solution Approach 1:
The same clock signal terminal is multiplexed to control multiple cache units across different repeat units. This multi-functionality approach reduces the total number of clock signal terminals needed, simplifying the circuit structure. The control circuits manage the timing by selectively enabling data copying between cache units based on the clock signal phase.
Solution Approach 2:
The clock signal operates periodically to control the sequential operation of cache units. By using periodic clock cycles, the system coordinates data storage and copying operations across multiple cache units, ensuring proper timing without requiring complex individual control signals for each cache unit.
3Device complexity
If low-resolution signal sources are used to drive high-resolution panels, then the cost is reduced, but the image resolution would normally deteriorate
Solution Approach 1:
The patent uses multiple repeat units of cache structures to create an additional dimensional space for data replication. Low-resolution data from the signal source is expanded across multiple cache units through systematic copying, effectively transforming the data density to match high-resolution panel requirements without increasing the signal source resolution.
Solution Approach 2:
Display data is pre-processed and stored in cache units before being output to the display panel. This preliminary caching and copying action allows the system to prepare high-resolution data from low-resolution sources in advance, ensuring that the final output maintains high resolution even though the original signal source has lower resolution.
Data Source
AI summary
A display panel, including a drive circuit, where the drive circuit is at least used to drive the display panel to display obtained display data. The drive circuit includes a shift register, a data buffer and a first control circuit; the shift register is used to output display data of each sub-pixel according to a preset timing sequence; the data buffer at least includes a first cache module composed of N repeat units; a repeat unit includes at least one cache unit, the cache unit is connected to the shift register, and two cache units at a same position in the k-th repeat unit and the (k+1)-th repeat unit are multiplexed with a same clock signal terminal; the cache unit is used to be turned on in response to an output signal from the clock signal terminal connected to the cache unit, to cache the received display data.