Display Panel Gate Drive Groups for Tri-Gate DLG Scanning
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Solution Overview
Problem
The Dual Line Gating (DLG) technique is difficult to implement in display panels with tri-gate drive architectures due to the non-adjacent scanning requirements of sub-pixel rows, leading to challenges in designing the drive circuit and causing vertical dark bands.
Innovation Solution
A display panel design with alternating odd and even-numbered pixel rows and columns, utilizing a gate drive circuit with multiple gate drive groups that alternate or synchronously scan sub-pixel rows/columns to achieve DLG mode, reducing the number of data lines and driver chips, and minimizing resistance differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If Dual Line Gating technique is implemented in tri-gate drive architecture, then cost and power reduction are achieved by reducing effective resolution, but the implementation becomes difficult due to non-adjacent scanning requirements of sub-pixel rows
Solution Approach 1:
The gate drive circuit is segmented into multiple independent gate drive groups, where each group is responsible for scanning a specific set of sub-pixel rows. This segmentation allows the circuit to handle non-adjacent scanning requirements by dividing the display panel into manageable sections, thereby reducing implementation difficulty while maintaining power savings from DLG mode.
Solution Approach 2:
The gate drive circuit is designed with dynamic switching capability between different scanning modes (adjacent and non-adjacent). By dynamically reconfiguring the gate drive groups based on the required scanning pattern, the circuit can implement DLG technique in tri-gate architecture without requiring complete redesign, thus reducing complexity while achieving power reduction.
2Loss of energy
If Dual Line Gating technique is implemented in tri-gate drive architecture, then cost reduction is achieved by reducing effective resolution, but vertical dark bands appear due to non-adjacent scanning requirements
Solution Approach 1:
Buffer circuits are introduced as intermediary elements between the gate drive groups and the sub-pixel rows. These buffer circuits ensure uniform signal distribution and timing synchronization across non-adjacent rows, preventing the formation of vertical dark bands while enabling cost-effective DLG implementation in tri-gate architecture.
Solution Approach 2:
The gate drive circuit parameters such as scanning frequency, pulse width, and voltage levels are dynamically adjusted based on the scanning mode. By changing these parameters appropriately when switching between adjacent and non-adjacent scanning, the circuit maintains uniform brightness across the display panel while achieving the cost benefits of reduced effective resolution.
3Adaptability or versatility
If multiple gate drive groups are used to scan sub-pixel rows, then DLG mode implementation is enabled in tri-gate architecture, but the number of data lines and driver chips increases
Solution Approach 1:
Each gate drive group is designed with multi-functionality to handle both adjacent and non-adjacent scanning modes, as well as both DLG and full-resolution modes. This universality allows the same hardware infrastructure to support multiple operating modes without requiring additional dedicated components, thereby enabling DLG compatibility while minimizing the increase in data lines and driver chips.
Solution Approach 2:
Multiple gate drive groups are merged into a unified control structure that shares common control signals and timing mechanisms. By combining the functionality of multiple groups under a single control framework, the system achieves DLG mode compatibility without proportionally increasing the number of independent driver chips and data lines.
4Productivity
If gate drive groups synchronously scan odd and even pixel rows, then high refresh frequency is achieved, but the scanning complexity increases
Solution Approach 1:
The gate drive groups employ periodic scanning patterns where odd and even pixel rows are scanned in alternating cycles. This periodic action enables high refresh frequency by ensuring that all rows are updated within each frame period, while the regularity of the pattern simplifies the control logic compared to arbitrary scanning sequences.
Solution Approach 2:
The gate drive circuit performs preliminary setup of scanning sequences and timing parameters before actual display operation. By pre-configuring the scanning patterns for odd and even rows, the system achieves high refresh frequency with simplified runtime control, as the complex sequencing decisions are made in advance rather than in real-time.
Data Source
AI summary
A display panel includes: multiple pixel rows including multiple odd-numbered pixel rows and multiple even-numbered pixel rows arranged alternately in sequence in a column direction, each of the pixel rows including three adjacent sub-pixel rows; multiple data lines, each of the data lines being connected to a sub-pixel column of the display panel; multiple scan lines, each of the scan lines being connected to one of the sub-pixel rows; and a gate drive circuit connected to the plurality of scan lines.