Display Panel Drive IC Layout for Uniform Voltage Charging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices experience uneven voltage charging across the display panel due to differences in delay times of data and gate signals, leading to inconsistent pixel performance.
Innovation Solution
The display device is divided into blocks with drive ICs biased towards the left and right sides, and the phase of the clock is shifted or the data voltage is delayed to match the delay time of the clock and scan pulses, reducing the margin time between data voltage and scan pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single drive IC is used to supply data voltage to the entire display panel, then the device complexity is reduced, but the voltage charging uniformity across different positions deteriorates
Solution Approach 1:
The display panel is divided into multiple blocks (first block, second block, third block, fourth block) along the first direction, with each block served by a dedicated drive IC (first drive IC, second drive IC, third drive IC, fourth drive IC). This segmentation allows independent optimization of data signal transmission paths for each block, enabling uniform voltage charging across the entire display panel by compensating for position-dependent delay differences.
2Device complexity
If drive ICs are positioned at the center of the display panel, then the connection structure is simplified, but the delay time difference between left and right positions increases
Solution Approach 1:
The drive ICs are positioned asymmetrically relative to the display panel blocks they serve. Specifically, the first drive IC is disposed to be biased toward the left end within the first block, the second drive IC is disposed to be biased toward the right end within the second block, the third drive IC is disposed to be biased toward the left end within the third block, and the fourth drive IC is disposed to be biased toward the right end within the fourth block. This asymmetric positioning compensates for the delay time differences caused by signal transmission distances, achieving uniform delay characteristics across left and right positions.
3Productivity
If link lines are made shorter to reduce delay time, then the productivity is improved, but the coverage area of each drive IC is reduced
Solution Approach 1:
The display panel is divided into multiple blocks, each served by a dedicated drive IC. This segmentation allows each drive IC to cover a smaller area with shorter link lines, reducing signal transmission delay and improving productivity, while still achieving full panel coverage through the distributed architecture of multiple drive ICs.
Data Source
AI summary
The present disclosure relates to a display device. The display panel of the display device includes at least a first block, a second block, a third block, and a fourth block from the left. A data driver includes a first drive IC disposed to be biased to the left end of the display panel within the first block of the display panel; and a second drive IC disposed to be biased to the right end of the display panel within the fourth block of the display panel.