Display Panel Driving Method for Crosstalk Reduction
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Solution Overview
Problem
Large-size display products, such as high-end TVs, experience poor display issues like horizontal crosstalk and line image sticking due to significant differences in gray scale values between adjacent rows of pixel units during data signal switching.
Innovation Solution
A method for driving a display panel that involves determining the difference in gray scale values between adjacent rows of pixel units and adjusting the phase of the clock signal for the affected shift register to delay the falling edge of the pull-up node, thereby outputting a scanning signal with a delayed phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data signals are switched between high and low gray scales in large-size display products, then display flexibility and adaptability are improved, but horizontal crosstalk and line image sticking occur causing display quality degradation
Solution Approach 1:
The patent applies preliminary action by pre-charging the pull-up node of the shift register before the data signal switching occurs. When a gray scale transition is detected, the clock signal phase is adjusted to extend the charging time of the pull-up node, ensuring it is properly charged before the next scanning operation. This prevents horizontal crosstalk and line image sticking by preparing the circuit in advance, thus maintaining display quality while allowing flexible gray scale switching.
2Reliability
If the charging time of pixel units is extended to prevent image sticking, then display quality is improved, but scanning speed and refresh rate decrease
Solution Approach 1:
The patent applies dynamics by making the clock signal phase adjustable rather than fixed. The system dynamically changes the phase of the clock signal based on the detected gray scale transition needs. When gray scale switching occurs, the clock phase is adjusted to extend charging time; when no switching occurs, the clock phase returns to normal, maintaining high scanning speed. This dynamic adjustment resolves the contradiction between display quality and scanning speed.
Solution Approach 2:
The patent applies parameter changes by modifying the clock signal phase parameter in response to gray scale transitions. The phase parameter is changed from its normal value to a delayed value when charging extension is needed, and reverted when not needed. This parameter adjustment allows the system to extend charging time only when necessary, preventing display defects without permanently reducing scanning speed.
3Reliability
If the clock signal phase is adjusted to delay the falling edge of the pull-up node, then horizontal crosstalk is reduced, but the complexity of signal control increases
Solution Approach 1:
The patent applies feedback by detecting the gray scale transition status and using this information to control the clock signal phase adjustment. The system continuously monitors whether data signals are switching between high and low gray scales, and based on this feedback, automatically adjusts the clock phase to extend charging time when needed. This feedback mechanism simplifies the control logic compared to complex predetermined timing schemes, as the system only adjusts phases when actually needed, thereby maintaining signal integrity without excessive complexity.
Data Source
AI summary
A display panel driving method, a display panel and a display apparatus. The display panel driving method comprises: according to a data signal transmitted in a data line, determining whether a grayscale value difference of a data signal input by a pixel unit of an nth row and a data signal input by a pixel unit of an (n−1)th row is greater than a threshold, n being a positive integer less than or equal to N; if the grayscale value difference between the data signal input by the pixel unit of the nth row and the data signal input by the pixel unit of the (n−1)th row is greater than the threshold, then adjusting the phase of a clock signal input by the nth shift register, such that the falling of the pull-up node of the nth shift register is delayed along with time, to output a phase-delayed scan signal.