Display Panel Driving Device ESD Protection Circuit Design
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Solution Overview
Problem
The existing TFT-LCD driving devices face challenges in enhancing electrostatic discharge (ESD) protection capability while maintaining cost-effectiveness, as the ESD protection capability is directly proportional to the area of the electrostatic discharge diode, leading to increased costs with larger diode areas.
Innovation Solution
A driving device for display panels incorporates a protection circuit with multiple first diodes connected in parallel at the chip input ends and a larger third diode with its cathode connected to the first diode's anode, grounded, and optionally a second diode for enhanced reverse breakdown voltage, allowing for improved ESD protection with reduced total diode area and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of electrostatic discharge diode is increased to improve ESD protection capability, then the ESD protection capability is improved, but the cost of the chip is increased
Solution Approach 1:
The protection circuit is divided into multiple diodes with different functions: first diodes (D1) for basic ESD protection at each input end, a second diode (D2) for voltage level conversion and isolation, and a third diode (D3) with large area for enhanced ESD energy dissipation. This segmentation allows each diode to be optimized for its specific function, achieving high ESD protection without requiring all diodes to have large areas.
Solution Approach 2:
Different diodes in the protection circuit have different area specifications tailored to their local functions. The third diode (D3) has a significantly larger area (≥10 times) compared to the first diodes (D1), while the second diode (D2) has an area equal to the first diodes. This local differentiation of diode areas optimizes the overall ESD protection capability while controlling the total chip area and cost.
2Reliability
If the area of electrostatic discharge diode is increased to improve ESD protection capability, then the ESD protection capability is improved, but the occupied space on the chip is increased
Solution Approach 1:
The protection circuit segments the ESD protection function across multiple diodes with different area allocations. Only the third diode (D3) requires a large area for effective ESD energy dissipation, while the first diodes (D1) and second diode (D2) use smaller areas. This segmentation concentrates the area requirement to a single diode rather than distributing large areas across all diodes, reducing the total chip area occupation.
Solution Approach 2:
The circuit implements local quality by assigning different area characteristics to different diodes based on their specific functions. The third diode (D3) located at the output end has a large area for ESD energy handling, while the input-end first diodes (D1) and the intermediate second diode (D2) have smaller areas. This localized area allocation achieves effective ESD protection with minimized total chip area occupation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances ESD protection capability by directing electrostatic discharge energy to ground through the high-capability third diode, while minimizing the overall diode area and thus the cost, without compromising the occupied space or performance.
Implementation Method 1
the ESD protection capability of the chip is proportional to the area of electrostatic discharge diode
Implementation Method 2
a third diode, a cathode of the third diode connects to an anode of the first diode, an anode of the third diode is grounded
Data Source
AI summary
The present disclosure provides a driving device of the display panel, which includes a protection circuit in a chip, the protection circuit includes: a plurality of chip input ends; a plurality of first diodes (D1) connected to the plurality of chip input ends in parallel, the cathodes of the first diodes (D1) connect to the chip input ends; a third diode (D3), a cathode of the third diode (D3) connects to an anode of the first diode (D1), an anode of the third diode (D3) is grounded, an area of the third diode (D3) is larger than an area of the first diode (D1), an amount of the third diode (D3) is less than an amount of the first diode (D1).