Display Panel Driving Method for RC Delay Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Large-sized liquid crystal display panels experience RC time delay in gate and data signals, leading to decreased charging ratio and quality issues such as luminance reduction, color mixing, and ghosting due to the RC time delay.
Innovation Solution
A method of driving a display panel by providing data signals with alternating polarities to data lines during odd and even frames, with clock signals having different rising times and phase angles determined by the RC delay time, to minimize the impact of RC time delay on charging ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the display panel size is increased, then the display area is improved, but RC time delay increases causing charging ratio degradation
Solution Approach 1:
The patent segments the data signal transmission by applying different clock signals to different data lines. Specifically, first clock signals are applied to first data lines while second clock signals are applied to second data lines, allowing independent timing control for different regions of the display panel. This segmentation enables compensation for RC time delay variations across different areas of the large display panel.
Solution Approach 2:
The patent implements local quality by making the clock signal characteristics data line-specific. Each data line receives a clock signal with timing parameters optimized for its specific position and RC characteristics. The output timing of data signals is adjusted based on local RC delay conditions, ensuring uniform charging ratios across different regions of the display panel.
2Speed
If data signals are provided to all data lines simultaneously, then the data transmission speed is improved, but charging ratio difference between adjacent data lines increases
Solution Approach 1:
The patent introduces dynamic timing adjustment by using multiple clock signals with different rising times and phase angles. The timing of data signals is dynamically adjusted based on the specific data line and frame type (odd or even frames). This dynamic approach maintains high data transmission speed while compensating for RC delay differences, ensuring uniform charging ratios across adjacent data lines.
Solution Approach 2:
The patent implements periodic action by alternating between different clock signal configurations for odd-numbered and even-numbered frames. During odd frames, first clock signals are used for first data lines while second clock signals are used for second data lines. During even frames, the assignment is reversed. This periodic switching compensates for RC delay variations while maintaining continuous high-speed data transmission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces display quality degradation caused by charging ratio differences between positive and negative polarities, improving the overall display quality by adjusting the output timing of data signals based on the RC delay time.
Implementation Method 1
a RC time delay of the gate signal transferred through a gate line and the data signal transferred through a data line occurs when a liquid display panel has a large size
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A method of driving a display panel includes providing a positive polarity data signal to a first data line during an odd-numbered frame, and providing a negative polarity data signal to the first data line during an even-numbered frame. The positive polarity data signal has a first polarity. The negative polarity data signal has a second polarity. Output timing of the positive polarity data signal is different from output timing of the negative polarity data signal.