Display Panel Driving Method for Smear Reduction

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Solution Overview

Problem

Organic light-emitting display devices suffer from a smear phenomenon due to the hysteresis effect of driving transistors, which affects the display screen's ability to quickly switch between frames, especially at high frequencies, leading to display quality issues.

Innovation Solution

The display panel employs a pixel driving circuit with a first reset stage, a data writing stage, and a light-emitting stage, utilizing two pulse width modulation periods with different duty cycles, where the time interval between the start of the first reset stage and the data writing stage is extended in the second pulse period with a low duty cycle, allowing for longer threshold compensation and characteristic recovery time of the driving transistor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the refresh rate is increased to achieve high-frequency display, then the display update speed is improved, but the smear phenomenon becomes more prominent due to insufficient transistor recovery time

Engineering Contradiction:
Improvedisplay update speedVSAvoidsmear phenomenon
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by performing a first reset stage before the data writing stage to compensate for transistor threshold voltage shifts. This preliminary reset action ensures the transistor is in a known initial state before new data is written, preventing smear effects during high-frequency display updates.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the timing parameters of the pixel driving circuit by introducing different time intervals for different duty cycles. Specifically, when the duty cycle is less than a threshold value, the time interval between the first reset stage and data writing stage is extended to compensate for insufficient recovery time, thereby reducing the smear phenomenon while maintaining high refresh rates.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the time interval between reset stage and data writing stage is extended to improve transistor recovery, then the characteristic recovery is improved, but the overall display response time increases

Engineering Contradiction:
Improvetransistor characteristic recoveryVSAvoiddisplay response time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the time interval between the first reset stage and data writing stage variable rather than fixed. The time interval is dynamically adjusted based on the duty cycle: when the duty cycle is lower, the time interval is extended to ensure adequate recovery; when the duty cycle is higher, the time interval is reduced to maintain faster response. This dynamic adjustment resolves the contradiction between recovery quality and response speed.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20240233648A9Display panel driving method and display panel
Publication Date: 2024.07.11 WUHAN TIANMA MICRO ELECTRONICS CO LTD
  • US20240233648A9 patent drawing
  • US20240233648A9 patent drawing
  • US20240233648A9 patent drawing

AI summary

A display panel including a first pulse width modulation period and a second pulse width modulation period, in the first pulse width modulation period, a duty cycle of a light-emitting control signal in a light-emitting stage being a first duty cycle, in the second pulse width modulation period, the duty cycle of the light-emitting control signal in the light-emitting stage being a second duty cycle, the first duty cycle being greater than the second duty cycle, in the first pulse width modulation period, a time interval between the start time of the first reset stage and the start time of the data writing stage being t1, in the second pulse width modulation period, the time interval between the start time of the first reset stage and the start time of the data writing stage being t1, t1<t2.