Display Panel Driving Structure Using Lower-Bit Clock Signals
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Solution Overview
Problem
Existing display panel technologies require higher bit counts for display clock signals, leading to increased operating frequency, dynamic power consumption, and component area, which results in larger system volume and load.
Innovation Solution
A driving structure that adjusts the frequency of the display clock signal to match the number of bits in the pixel data, allowing lower bit display clock signals to achieve higher bit data resolution while reducing power consumption and component area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If higher bit display clock signals are used to achieve higher bit data resolution, then data resolution capability is improved, but operating frequency increases
Solution Approach 1:
The patent changes the parameter of clock signal bit depth while maintaining the same operating frequency. By using lower bit clock signals (e.g., 8-bit) with extended timing cycles, the system achieves higher bit data resolution (e.g., 14-bit) without increasing operating frequency, thus resolving the contradiction between resolution and speed
2Measurement precision
If higher bit display clock signals are used to achieve higher bit data resolution, then data resolution capability is improved, but dynamic power consumption increases
Solution Approach 1:
The patent reduces dynamic power consumption by using lower bit clock signals instead of higher bit signals. Since dynamic power is directly proportional to bit depth, using 8-bit clock signals to achieve 14-bit data resolution through extended timing reduces the power required for clock signal generation and transmission while maintaining the same data resolution capability
3Measurement precision
If higher bit display clock signals are used to achieve higher bit data resolution, then data resolution capability is improved, but area of electronic components increases
Solution Approach 1:
The patent reduces the area of electronic components by using lower bit clock signals. Since the area of clock signal components (such as buffers and drivers) is directly related to bit depth, using 8-bit clock signals instead of 14-bit signals significantly reduces component area while achieving the same 14-bit data resolution capability through extended timing cycles
4Measurement precision
If higher bit display clock signals are used to achieve higher bit data resolution, then data resolution capability is improved, but volume of system increases
Solution Approach 1:
The patent reduces system volume by using lower bit clock signals. Since the volume of electronic components is directly proportional to their area and bit depth requirements, using 8-bit clock signals to achieve 14-bit data resolution reduces the overall volume of the display panel system while maintaining the same data resolution capability
Data Source
AI summary
The present application discloses a driving structure for display panel, which comprises a controller and at least one driver. The controller is disposed on a display panel, the controller generates a data signal and a display clock signal. The at least one driver is disposed on a display panel, the at least one driver receives the data signal and a display clock signal, the controller adjusts a frequency of the display clock signal to correspond the data signal.