Display Panel Driving Method Synchronizing Gate Signals
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Solution Overview
Problem
In large-size or high-resolution display devices, traditional methods face synchronization challenges and delays in gate driving signals due to the limitations of single signal processing chips, leading to increased production costs from the need for multiple chips and frame memory units for coordination.
Innovation Solution
Implementing at least two time sequence controllers for each display area, which obtain synchronization signals based on display signals to adjust the starting times of scanning signals, ensuring synchronization across all display areas without the need for additional memory units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single signal processing chip is used to control the gate driving circuit, then the system structure is simple, but it cannot process large amounts of signals simultaneously for large-size or high-resolution display panels
Solution Approach 1:
The patent divides the display panel into multiple display areas, each controlled by a separate signal processing chip. Each chip processes signals for its designated display area independently, enabling parallel processing of large amounts of signals simultaneously while maintaining manageable system complexity through modular architecture.
2Reliability
If frame memory units are added to each chip for coordination, then synchronization among multiple chips is achieved, but production cost increases due to additional memory components
Solution Approach 1:
The patent merges the synchronization function into the existing SPI communication interface between chips. Instead of adding separate frame memory units, the chips share a common timing reference through the SPI bus, allowing coordination and synchronization to be achieved using the already-present communication infrastructure, thereby avoiding additional memory components and reducing production costs.
3Area of stationary object
If multiple chips are used to control different display areas, then the display panel can be driven, but time delay and different transmission paths cause synchronization problems in gate driving signals
Solution Approach 1:
The patent establishes a common timing reference level for all signal processing chips through the SPI communication bus. By synchronizing the clock signals and timing references across all chips, the system creates an equipotential timing state where all chips operate from the same time baseline, eliminating cumulative delays and ensuring synchronized gate driving signals across all display areas despite different transmission paths.
Data Source
AI summary
The embodiments of the present invention provide a display panel driving method, a driving device and a display device, which can improve the time delay of the gate driving signals of a partitioned controlled display panel and reduce the production cost. The display panel comprises at least two time sequence controllers and at least two display areas, each of the time controllers corresponding to one of the display areas respectively; the driving method comprises each of the time sequence controllers obtaining a synchronization signal according to an obtained display signal of the corresponding display area, the synchronization signal comprising a starting time of a first line of scanning signals of the corresponding display area, the time sequence controllers adjusting the starting times of the first lines of the scanning signals according to the synchronization signals of at least one display area so as to make the starting times of the first lines of the scanning signals of all display areas are the same.