Light-Emitting Display Panel with Stacked Capacitor and Dual Gate TFT

The patent applies dimensionality change by transitioning from a planar conductor layout to a three-dimensional stacked structure. Multiple conductors are arranged in different layers (first conductor layer, second conductor layer, third conductor layer) vertically stacked above each other. This vertical stacking enables the conductors to occupy different spatial dimensions, thereby increasing the effective conductor area for improved performance while maintaining a compact footprint that preserves the aperture ratio.

The patent implements nesting by placing conductors within conductors or stacking them in nested layers. The first, second, and third conductors are positioned in overlapping horizontal projections, creating a nested configuration where conductors are embedded within the vertical space occupied by others. This nested arrangement maximizes the use of available space, allowing multiple conductors to coexist in a compact area without significantly increasing the overall footprint.

The patent applies dimensionality change by arranging capacitor conductors in multiple vertical layers rather than expanding them horizontally. The first, second, and third conductors are stacked vertically with their horizontal projections overlapping or partially overlapping. This vertical stacking increases the effective capacitor area for improved charging efficiency while maintaining a compact horizontal footprint that preserves the opening size for light emission.

The patent merges the functions of multiple conductors by arranging them in overlapping configurations. The first, second, and third conductors are positioned such that their horizontal projections overlap, allowing them to share the same horizontal space. This merging approach enables the capacitor to achieve higher charging efficiency through increased conductor area without proportionally increasing the overall device area, thus preserving the opening size.