Display Panel Dual-Sided Source Driving Chip Pin Arrangement
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Solution Overview
Problem
The poor bonding of flexible printed circuit boards in display panels affects the usability and viewing experience due to inefficient pin utilization and spacing, leading to reduced bonding yield.
Innovation Solution
The display panel design includes a substrate with active and non-active areas, where signal lines are connected to source driving chips with pins on both sides, allowing for symmetrical and scattered connections to maximize pin usage, increasing the spacing between pins and bonding area without adding more source driving chips, and using metal layers to route signal lines without interfering with data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source driving chips with pins on one side only are used, then the device complexity is reduced, but the bonding area is insufficient leading to poor bonding quality
Solution Approach 1:
The source driving chip transitions from single-sided pin arrangement to dual-sided pin arrangement, utilizing both sides of the chip for pin placement. This dimensional change in pin distribution significantly increases the available bonding area and improves bonding quality while maintaining manageable device complexity through symmetric design
2Reliability
If more source driving chips are added to increase pin count, then the bonding area increases, but the device complexity and cost increase
Solution Approach 1:
Multiple pin functions are integrated into a single source driving chip by utilizing dual-sided pin arrangements. This merging approach consolidates what would otherwise require multiple separate chips into one component, increasing bonding area and yield while reducing overall device complexity and component count
3Adaptability or versatility
If signal lines are routed through metal layers, then the signal line layout flexibility is improved, but the manufacturing precision requirements increase
Solution Approach 1:
Signal lines are routed through vertical through holes in metal layers, utilizing the third dimension (depth) for signal transmission. This allows flexible planar routing while managing complexity through structured multi-layer design, balancing routing flexibility with manufacturable precision requirements
Data Source
AI summary
This application discloses a display panel and a display device. The display panel includes a substrate, source driving chips, and gate chips. The source driving chip includes two sets of pins. The two sets of pins are respectively located on a first side and a second side of a same source driving chip. The gate chips are connected to different sets of pins.