Display Panel ESD Protection via Resistance Structure
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Solution Overview
Problem
Display panels using inorganic light-emitting devices are vulnerable to damage from static electricity during manufacturing, particularly due to electrostatic discharge (ESD) currents flowing through test lines, which can cause circuit damage.
Innovation Solution
A resistance structure is integrated into the display panel, featuring vertical interconnect accesses (vias) and a resistance layer with higher resistance than the test line material, allowing ESD currents to be diverted and preventing damage to the circuit. This structure is formed within the layer structure on the test pattern, eliminating the need for a separate resistance element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a test line is provided on the substrate for testing purposes, then manufacturing and testing capability is improved, but the circuit becomes vulnerable to static electricity damage
Solution Approach 1:
A resistance structure is introduced as an intermediary element between the test line and the pixel circuit. This resistance structure includes a resistance layer with higher resistance than the test line material, positioned to intercept ESD currents before they reach the pixel circuit. The structure acts as a protective mediator that allows normal testing while blocking harmful static discharge currents.
Solution Approach 2:
The resistance structure is locally positioned at specific locations where ESD protection is most needed, such as near the pixel circuit or at strategic points along the test line. The insulating layer is provided only in specific areas to create the resistance structure, while other areas maintain the original test line characteristics for proper testing functionality.
2Reliability
If a resistance structure with higher resistance material is integrated into the test line, then ESD protection is improved, but the test line structure complexity increases
Solution Approach 1:
The resistance structure is merged with the existing test line structure by integrating it into the same layer system. The resistance layer is formed as part of the test line assembly, sharing the same substrate and interconnection architecture. This merging approach adds ESD protection functionality without requiring a completely separate structural system.
Solution Approach 2:
The resistance structure utilizes composite material construction, combining an insulating layer with conductive material to form a structure that has higher resistance than the pure metal test line material. This composite approach enables the resistance function while maintaining compatibility with standard semiconductor manufacturing processes.
3Reliability
If the test line is made discontinuous with vias and resistance layer, then ESD current path is controlled, but manufacturing precision requirements increase
Solution Approach 1:
The test line is segmented into discrete sections separated by insulating layers and vias. Instead of a continuous conductive path, the test line is divided into segments connected through vertically stacked vias. This segmentation provides natural interruption points for ESD current while maintaining electrical connectivity for normal testing operations.
Solution Approach 2:
The discontinuity in the test line is resolved by transitioning to another dimension - vertical vias connect horizontal test line segments through the insulating layer. This dimensional transition allows the test line to be discontinuous in the planar direction while maintaining continuity through the vertical dimension, providing ESD protection without compromising electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The resistance structure effectively protects the display panel circuits from ESD-induced damage, ensuring reliable operation and preventing static electricity from affecting the pixel circuits during manufacturing and subsequent processes.
Implementation Method 1
a resistance layer provided on the insulating layer and extending between the at least two vias, wherein the at least two vias connect the test line and the resistance layer to each other
Data Source
AI summary
A display panel in which a resistance structure is provided on a test pattern to prevent a circuit of the display panel from being damaged by static electricity introduced into the test pattern, and a display apparatus having the same are provided. The display panel includes: a substrate; a plurality of pixel circuits provided on the substrate and configured to drive a plurality of inorganic light emitting devices; a test line provided on the substrate and extending from an edge of the substrate; an insulating layer provided on the test line; and a resistance structure provided on the test line, the resistance structure including: at least two vertical interconnect accesses (vias) passing through the insulating layer, and a resistance layer provided on the insulating layer and extending between the at least two vias, wherein the at least two vias connect the test line and the resistance layer to each other, and the test line is discontinuous at an area between the at least two vias, and wherein the resistance layer is configured to receive, through one of the at least two vias, a current applied to the test line.