Display Panel Fan-Out Line Overlap for Signal Consistency
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Solution Overview
Problem
In display technologies, the phenomenon of split screen occurs due to parasitic capacitance and differences in signal aspects between left and right clock signals, which affects the data signal value and screen occupancy ratio.
Innovation Solution
A display panel design that includes data lines, bonding terminals, fan-out lines, and demuxes with switch transistors and clock signal lines, where each fan-out line overlaps each clock signal line for an equal number of times to maintain signal consistency and reduce the width of the step area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fan-out lines completely avoid overlapping with clock signal lines, then signal interference is reduced, but screen occupancy ratio decreases and step area width increases
Solution Approach 1:
The patent converts the harmful parasitic capacitance effect into a beneficial shielding mechanism. By intentionally allowing fan-out lines to overlap with clock signal lines, the clock signal lines act as shield plates that generate an electric field to counteract the coupling from data lines, transforming the previously harmful capacitive coupling into a useful shielding effect that maintains signal stability while enabling tighter line spacing
Solution Approach 2:
The patent changes the electrical parameters of the clock signal lines by applying specific voltage levels (first voltage or second voltage) to create different electric field strengths. This parameter change allows the clock signal lines to function as active shields that can dynamically adjust their shielding capability, enabling the fan-out lines to overlap with clock signal lines without suffering from harmful parasitic capacitance effects
2Length of stationary object
If demux is turned off to maintain data signal potential by capacitance, then data line width is reduced, but data signal becomes vulnerable to clock signal jumps due to parasitic capacitance
Solution Approach 1:
The patent converts the harmful parasitic capacitance between data lines and clock signal lines into a beneficial shielding effect. By keeping the demux turned off and allowing the data line to float while maintaining it as a shield plate, the data line's electric field counteracts the coupling from clock signal lines, transforming the previously harmful capacitive coupling into a useful shielding effect that protects the data signal from clock signal jumps
Solution Approach 2:
The patent applies preliminary action by pre-establishing the data line as a shield plate before the clock signal writing operation. The data line is maintained at a specific voltage level (first voltage or second voltage) in advance, creating a protective electric field that preemptively counteracts the parasitic capacitance coupling from subsequent clock signal writes, preventing signal distortion before it occurs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the risk of split screen by ensuring consistent signal aspects across all data lines, thereby improving screen occupancy ratio and display stability without completely avoiding overlapping between data lines and clock signals.
Implementation Method 1
due to the parasitic capacitance, if the clock signal jumps, the data signal value will be influenced
Data Source
AI summary
The present disclosure provides a display panel and display device. The display panel includes: data lines disposed in a display area; a bonding terminal disposed in a non-display area surrounding the display area; fan-out lines; and demuxes disposed between the display area and the bonding terminal; each of the demuxes comprises at least two switch transistors; each switch transistor in one demux has a first electrode electrically connected to a corresponding data line of the data lines through a first connection line, a second electrode connected to the bonding terminal through one of the fan-out lines corresponding to the one demux, and a gate electrode electrically connected to a first clock signal line corresponding to the switch transistor; each fan-out line of the display panel overlaps the first clock signal line for an equal number of times.