Display Panel TFT Layout With Fewer Photomasks
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Solution Overview
Problem
The manufacturing process of thin-film transistor array substrates requires multiple photomasks, leading to higher production costs, complexity, and time due to the need for eight photomasks to form the structure, which increases costs and complexity.
Innovation Solution
A display panel design that integrates a first conductive layer with a data line and light-shielding portion, a semiconductor layer with an active portion and functional electrode, and a second conductive layer with electrode members, allowing for the elimination of an additional photomask to fabricate a capacitor plate, reducing the number of photomasks required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photomasks are used to form the array substrate structure, then the manufacturing precision and structural complexity are improved, but the production cost and process time increase
Solution Approach 1:
The patent merges the formation of the capacitor plate with the formation of the pixel electrode into a single photomask process. The second photomask is used to form both the pixel electrode pattern and the capacitor plate pattern simultaneously, eliminating the need for a separate photomask step and reducing overall process complexity while maintaining structural precision
Solution Approach 2:
The second photomask serves multiple functions: it defines the pixel electrode pattern, defines the capacitor plate pattern, and establishes the spatial relationship between these components. This multi-functional use of a single photomask reduces the total number of photomasks required while ensuring proper structural alignment
2Manufacturing precision
If eight photomasks are used to form the array substrate, then the manufacturing precision is improved, but the production cost increases
Solution Approach 1:
The patent combines the capacitor plate formation step with the pixel electrode formation step, both using the second photomask. This merging eliminates redundant photomask steps and reduces the total count from eight to six photomasks, directly lowering production costs while maintaining pattern accuracy through proper mask design
Solution Approach 2:
The patent extracts the capacitor plate formation requirement from the sequence of photomask steps and integrates it into the second photomask process. This extraction eliminates the need for additional dedicated photomask steps for capacitor plate formation, reducing costs while preserving the necessary structural precision
3Manufacturing precision
If eight photomasks are used for the array substrate structure, then the structural completeness is improved, but the process time increases
Solution Approach 1:
The patent merges multiple structural formation steps into fewer photomask processes. By using the second photomask to simultaneously define both the pixel electrode and capacitor plate, the total number of photomask steps is reduced, directly shortening the manufacturing process time while maintaining complete structural formation
Solution Approach 2:
The second photomask is designed to perform preliminary patterning for both the pixel electrode and capacitor plate in advance. This preliminary action establishes the positions of both components simultaneously, eliminating the need for subsequent separate patterning steps and reducing overall process time
Data Source
AI summary
Embodiments of this application provide a display panel, a method for preparing display panel, and a display device. The display panel includes a substrate; a first conductive layer disposed on the substrate and including a data line and a light-shielding portion; a semiconductor layer disposed on a side of the first conductive layer away from the substrate and including an active portion and a functional electrode spaced apart, the active portion including a channel portion as well as first and second contact portions connected to either side of the channel portion; and a second conductive layer disposed on a side of the semiconductor layer away from the first conductive layer and including first and second electrode members. The first electrode member is connected to the first contact portion and the data line, and a part of the second electrode member is connected to the second contact portion.