Display Panel Test Transistor Layout for Flicker Analysis
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Solution Overview
Problem
Existing display devices, particularly organic light emitting display devices, experience flicker phenomena due to variations in transistor operating characteristics when driving frequencies change, which are not accurately analyzed.
Innovation Solution
Incorporation of test transistors in a non-display area of the display panel to analyze the capacitance-voltage characteristics and reduce the influence of capacitance overlap, allowing for precise evaluation of transistor flicker characteristics by examining the interface characteristics of adjacent layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If test transistors are disposed in the display area, then the measurement of transistor characteristics can be performed, but the display area is reduced and the measurement accuracy is affected by interference with display elements
Solution Approach 1:
The patent divides the panel into distinct display area and non-display area, placing test transistors exclusively in the non-display area. This segmentation allows independent optimization of both display quality and measurement functionality without mutual interference.
Solution Approach 2:
The test transistor functionality is extracted from the display area and relocated to the non-display area. This extraction eliminates the conflict between measurement needs and display area requirements, allowing the display area to be maximized while maintaining measurement capabilities.
2Measurement precision
If conventional test transistors are used without considering overlap capacitance, then the device structure is simple, but the measurement accuracy of flicker characteristics is degraded due to capacitance influence
Solution Approach 1:
The patent applies different structural configurations to test transistors based on their specific measurement requirements. By optimizing the local structure of test transistors to minimize overlap capacitance effects, accurate flicker measurements are achieved without unnecessarily complicating the entire device architecture.
Solution Approach 2:
The patent modifies the structural parameters of test transistors, specifically adjusting the overlap region between gate electrodes and active layers, to minimize parasitic capacitance. This parameter optimization enables accurate flicker measurements while maintaining reasonable device complexity.
3Reliability
If multiple test transistors are added to improve measurement reliability, then the measurement accuracy improves, but the non-display area increases and manufacturing complexity increases
Solution Approach 1:
The patent combines multiple test transistors into an integrated test structure within the non-display area. By merging these test elements and sharing common circuitry and control signals, the patent achieves reliable measurements while minimizing the space required and simplifying the manufacturing process.
Data Source
AI summary
The present disclosure provides a display panel including a display area in which subpixels are disposed, and a non-display area outside of the display area in which an image is not displayed, and a display device including the display panel and a driving circuit configured to drive the display panel. The non-display area includes a test area in which a plurality of test transistors are disposed that correspond to a plurality of transistors included in the subpixels. An operating characteristic of the test transistors is detected which is representative of an operating characteristic of the transistors included in the subpixels.