Display Panel Clock Frequency Staging for Stable Pixel Signals
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Solution Overview
Problem
Display panels experience unstable output signals due to leakage currents, leading to issues such as uneven luminescence and flickering during grayscale switching, primarily caused by the continuous output of driving circuits at high frequencies and the accumulation of leakage currents during long holding stages.
Innovation Solution
Implementing a multi-stage holding stage with varying clock pulse frequencies, transitioning from a high frequency to lower frequencies to stabilize transistor states and reduce power consumption, including a first frequency for data writing, a second frequency for initial holding stages, and a third frequency for maintaining stability without excessive leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the driving circuit continuously outputs clock signals at high frequency during the holding stage, then the transistor state remains active and responsive, but leakage current accumulates and causes unstable output signals and flickering
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable rather than fixed. The frequency varies across different stages of the holding period, transitioning from higher to lower frequencies to adapt to the changing operational needs of the pixel circuit during different phases of the refresh cycle.
Solution Approach 2:
The patent implements periodic action by dividing the holding stage into multiple sub-stages with different clock frequencies. This periodic variation in frequency allows the system to maintain transistor activation during early holding stages and then reduce frequency as leakage current accumulates, preventing instability while managing power consumption.
2Loss of energy
If the clock pulse frequency is reduced during the holding stage, then power consumption decreases and leakage current accumulation is mitigated, but transistor state stability may be compromised
Solution Approach 1:
The patent applies segmentation by dividing the holding stage into multiple sub-stages (first holding stage, second holding stage, third holding stage) with different clock frequencies. This segmentation allows the system to optimize between power consumption and stability at different time points during the holding period.
Solution Approach 2:
The patent implements parameter changes by systematically varying the clock pulse frequency across different holding stages. The frequency transitions from F1 in the data writing stage to F2 in the first holding stage, then to F3 in subsequent holding stages, where F1>F2>F3≥0. This parameter variation allows the system to adapt transistor operation to minimize both power consumption and leakage current effects.
3Reliability
If the data refresh period includes multiple holding stages with varying frequencies, then signal stability improves and flickering is prevented, but the complexity of the control system increases
Solution Approach 1:
The patent applies dynamics by implementing a flexible frequency control mechanism that can adapt the clock signal frequency based on the current stage of the data refresh cycle. This dynamic adjustment is achieved through control circuits that receive stage information and accordingly adjust the frequency generated by frequency generation circuits.
Solution Approach 2:
The patent implements feedback by using stage determination circuits to monitor the current position in the data refresh cycle and provide this information to frequency control circuits. This feedback mechanism enables the system to automatically adjust clock frequencies based on real-time operational stage, managing complexity through intelligent control rather than fixed complex hardware.
Data Source
AI summary
A display panel includes a pixel circuit including a driving transistor, a driving circuit configured to provide a control signal to the pixel circuit, and a clock signal line configured to provide a clock signal for the driving circuit. The pixel circuit further includes a first transistor and a second transistor. The driving circuit includes a first driving circuit configured to provide a control signal to the first transistor, and a second driving circuit configured to provide a control signal to the second transistor. The clock signal line includes a first clock signal line configured to provide a first clock signal to the first driving circuit, and a second clock signal line configured to provide a second clock signal to the second driving circuit.