Display Panel Gate Clock Load Deviation Compensation
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Solution Overview
Problem
Conventional display panels with embedded gate driving circuits are prone to unexpected malfunctions and screen abnormalities due to potential issues with the gate driving circuit or abnormal load deviations between gate clock lines.
Innovation Solution
A display panel design that includes a substrate with a display area and a non-display area, where the gate driving circuit is embedded in the non-display area, and features a load deviation compensation pattern overlapping the gate clock lines to mitigate load deviations and prevent screen abnormalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate driving circuits are embedded in the display panel, then the number of components and bezel size are reduced, but screen abnormalities and malfunctions may occur
Solution Approach 1:
The patent introduces a compensation capacitor as an intermediary element that mediates between the gate clock line and ground to compensate for capacitive coupling effects. This capacitor acts as a mediator that balances the electrical characteristics, preventing screen abnormalities while maintaining the embedded gate driving circuit configuration that reduces bezel size.
Solution Approach 2:
The patent applies preliminary anti-action by pre-compensating for the capacitive coupling effect between gate clock lines and the cathode electrode. The compensation capacitor is designed in advance with a specific capacitance value that counteracts the harmful capacitive coupling, preventing screen abnormalities before they occur during display operation.
2Device complexity
If gate driving circuits are embedded in the display panel, then device integration is improved, but unexpected malfunctions may occur
Solution Approach 1:
The compensation capacitor serves as an intermediary that isolates and compensates for the electrical interference caused by the embedded gate driving circuit. By introducing this intermediate element, the patent prevents harmful capacitive coupling from causing malfunctions, thereby improving reliability without sacrificing the integration benefits.
Solution Approach 2:
The patent implements beforehand cushioning by pre-configuring the compensation capacitor to counteract potential electrical interference from the embedded gate driving circuit. This compensatory measure is built into the design before the device operates, cushioning against possible malfunctions and ensuring stable operation of the integrated circuit.
3Area of stationary object
If gate clock lines are disposed close to the cathode electrode, then area is reduced, but load deviation between gate clock lines increases
Solution Approach 1:
The patent applies local quality by making the electrical characteristics of gate clock lines non-uniform through selective compensation. The compensation capacitor is connected to specific gate clock lines that experience greater capacitive coupling, providing localized correction to balance the load distribution across all gate clock lines while maintaining their close proximity to the cathode electrode.
Solution Approach 2:
The patent changes the electrical parameters of the gate clock lines by introducing the compensation capacitor, which modifies the overall capacitance and electrical characteristics of the affected lines. This parameter change compensates for the increased capacitive coupling, maintaining balanced load distribution even when lines are disposed close to the cathode electrode for area reduction.
Data Source
AI summary
A display panel according to embodiments of the disclosure may comprise a substrate in which a display area and a non-display area are divided, a gate driving circuit disposed on the substrate and disposed in a gate driving circuit area within the non-display area, a plurality of gate clock lines disposed on the substrate and disposed in a first line area positioned outside the gate driving circuit area in the non-display area, an overcoat layer disposed on the plurality of gate clock lines and the gate driving circuit, a cathode electrode disposed in the display area and extending to the non-display area, and a load deviation compensation pattern overlapping the plurality of gate clock lines.