Display Panel Gate Driving With Cascaded Shift Registers
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Solution Overview
Problem
The driver circuit in existing display panels is unable to accurately drive rows of pixels due to insufficient charging duration of switch transistors, leading to inaccurate display brightness and overall display effect, particularly in larger panels with high resolution.
Innovation Solution
The driver circuit is redesigned with cascaded shift register units, where each shift register unit is connected to multiple scan lines, and the valid pulses of gate drive signals have a width greater than the driving time period, ensuring sufficient charging time for switch transistors in each row of pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the driver circuit uses conventional shift register units with one-to-one correspondence to scan lines, then the circuit structure is simple, but the charging duration of switch transistors is insufficient leading to inaccurate display brightness
Solution Approach 1:
The driver circuit is divided into multiple shift register units (first, second, third, and fourth shift register units), each responsible for driving specific scan lines. This segmentation allows each unit to independently control its assigned scan lines with sufficient charging duration, improving display brightness accuracy while maintaining manageable circuit complexity through modular design
Solution Approach 2:
The patent introduces a multi-dimensional mapping relationship where shift register units are cascaded in series (first to second, second to third, third to fourth) and each unit connects to multiple scan lines (first shift register unit to first and second scan lines, second to third and fourth, etc.). This dimensional transformation from simple one-to-one correspondence to a structured many-to-many relationship enables extended charging duration without excessive complexity
2Manufacturing precision
If the valid pulse width is increased to extend conduction time of switch transistors, then the charging duration is sufficient for accurate signal writing, but the driving speed of the driver circuit decreases
Solution Approach 1:
By segmenting the driver circuit into multiple shift register units that operate in a cascaded manner, each unit can maintain optimized pulse widths for its specific function. The segmentation allows the system to achieve both sufficient charging duration and maintained driving speed through distributed control architecture
Solution Approach 2:
The cascaded shift register units operate with periodic action, where each unit sequentially activates its scan lines with properly timed valid pulses. This periodic operation ensures that each switch transistor receives sufficient charging duration while the overall system maintains high driving speed through continuous sequential operation across multiple units
Data Source
AI summary
A display panel includes a driver circuit, multiple scan lines and multiple pixels arranged in an array. Gates of switch transistors in at least part of the same row of pixels are electrically connected to the same one scan line. In the driver circuit, the i-th shift register unit is cascaded with the (i+n)-th shift register unit; shift register units supply gate drive signals to the multiple scan lines respectively. The valid pulses of the gate drive signals each have a width denoted as T0; T0>(Th+k*Th), 0<k≤(n−1), and Th=1/(F*L), where F denotes the refresh rate of the display panel, and L denotes the number of rows of the multiple pixels; and valid pulses of gate drive signals output by any two adjacent shift register units have a shift amount greater than or equal to Th.