Display Panel Gate Line Driving Sequence Inversion
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Solution Overview
Problem
Half-source-double-gate type display panels experience vertical bright and dim stripes due to uneven brightness and dimness caused by the driving timing of old gate lines, which affects the frame quality.
Innovation Solution
The method involves driving the gate lines corresponding to the same scan line in different sequences during different image durations, ensuring that the voltage differences between the frame signal and the common potential are consistent across all sub-pixels, thereby mitigating the issue of vertical bright and dim stripes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the driving timing of old gate lines is used in half-source-double-gate type panels, then the number of source lines is reduced by half, but vertical bright and dim stripes occur due to uneven voltage differences
Solution Approach 1:
The patent applies dynamics by making the gate line driving sequence changeable across different image durations. Specifically, in odd image durations, gate lines are driven in the original sequence (G1, G2, G3, G4), while in even image durations, the sequence is inverted (G4, G3, G2, G1). This dynamic adjustment equalizes the voltage differences between frame signals and common potential across different scan lines, eliminating vertical bright and dim stripes while maintaining the reduced source line configuration.
Solution Approach 2:
The patent implements periodic action by alternating the gate line driving sequence between odd and even image durations. This periodic inversion ensures that no single scan line consistently experiences larger or smaller voltage differences, thereby distributing the luminance evenly across the display panel over time and preventing the formation of persistent vertical stripes.
2Device complexity
If the line inversion technique is adopted with alternating current common potential, then the panel can be driven with reduced source lines, but the voltage difference between frame signal and common potential varies across scan lines
Solution Approach 1:
The patent makes the gate line driving sequence dynamic by inverting it between odd and even image durations. This dynamic adjustment compensates for the varying voltage differences caused by line inversion technique and alternating current common potential, ensuring consistent luminance across all scan lines.
Solution Approach 2:
The patent changes the driving sequence parameter of gate lines based on image duration parity. By inverting the driving sequence in even image durations compared to odd image durations, the patent equalizes the effective voltage differences across different scan lines, thereby maintaining reliability in terms of voltage difference consistency.
3Device complexity
If the dot inversion technique is adopted with direct current common potential, then the panel structure is simplified, but vertical bright and dim stripes still occur due to inconsistent voltage differences
Solution Approach 1:
The patent applies dynamics by inverting the gate line driving sequence in even image durations while maintaining the original sequence in odd image durations. This dynamic adjustment equalizes the voltage differences across scan lines caused by dot inversion technique, eliminating vertical bright and dim stripes while preserving the simplified panel structure.
Solution Approach 2:
The patent implements periodic action by alternating the gate line driving sequence between odd and even image durations. This periodic inversion compensates for the inconsistent voltage differences introduced by dot inversion technique, ensuring uniform luminance across the display panel over time.
Data Source
AI summary
A method for driving a display panel is provided. The display panel includes a first scan line, and the first scan line includes sub-pixels. A first portion of the sub-pixels is controlled by a first gate line, and a second portion of the sub-pixels is controlled by a second gate line. The arrangement of the sub-pixels of the first portion and the second portion are in an interlaced arrangement. The method includes the following steps. First, drive the first gate line and then drive the second gate line in a first image duration. Then, drive the second gate line and then drive the first gate line in a second image duration.