Display Panel Gate Fan-Out Line Width Optimization

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Solution Overview

Problem

Conventional display panels experience long signal delays in gate fan-out lines due to their narrow width, leading to reduced charging efficiency and potential wrong charging of sub-pixels.

Innovation Solution

The display panel design includes gate fan-out lines with a width equal to or greater than the sum of the widths of two data lines and a gap, arranged in the same layer as data lines but different from scan lines, with via holes for electrical connection, and a light shielding layer to prevent coupling and optimize signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If the gate fan-out line width is kept narrow to achieve narrow border display, then the border width is reduced, but the signal delay increases and charging efficiency decreases

Engineering Contradiction:
Improveborder widthVSAvoidsignal delay
Core Design Contradiction:
Length of stationary objectVSLoss of time

Solution Approach 1:

The gate fan-out line is merged with two data lines to form a composite structure. The gate fan-out line width is designed to be equal to or greater than the sum of the widths of two data lines and the gap between them, effectively combining multiple conductive elements into one functional unit that reduces signal delay while maintaining narrow border appearance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The width parameter of the gate fan-out line is changed from a narrow single-line dimension to a wider composite dimension equivalent to two data lines plus gap. This parameter change increases the conductive cross-section and reduces signal delay without compromising the narrow border design goal.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the gate fan-out line width is increased to reduce signal delay, then the charging efficiency improves, but the border width increases

Engineering Contradiction:
Improvecharging efficiencyVSAvoidborder width
Core Design Contradiction:
ProductivityVSLength of stationary object

Solution Approach 1:

By merging the gate fan-out line with two data lines in a composite structure, the effective conductive width is increased to improve charging efficiency, while the overall border width remains controlled because the merged structure shares space with the data lines rather than adding separate width.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The gate fan-out line structure serves multiple functions: it acts as both a gate signal transmission line and combines with data lines for improved conductivity. This multi-functionality allows a single structure to achieve both narrow border appearance and high charging efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If the gate fan-out line is arranged in the same layer as data lines, then the manufacturing process is simplified, but electrical interference between lines may increase

Engineering Contradiction:
Improvemanufacturing process complexityVSAvoidelectrical interference
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The gate fan-out line is merged with two data lines in the same layer, creating a composite conductive structure. This merging simplifies the manufacturing process by reducing the number of separate patterning steps, while the integrated design actually reduces electrical interference by eliminating discrete interfaces between separate lines.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11335230B2Display panel
Publication Date: 2022.05.17 TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD
  • US11335230B2 patent drawing
  • US11335230B2 patent drawing

AI summary

The present application provides a display panel. The display panel includes multiple sub-pixels, multiple data lines, multiple scan lines, and multiple gate fan-out lines. Each two columns of the sub-pixels constitute a sub-pixel group, two data lines are arranged between the two columns of the sub-pixels in the sub-pixel group, and any two adjacent gate fan-out lines are spaced by at least one sub-pixel group. A width of the gate fan-out line is not less than a sum of widths of the two data lines in the sub-pixel group.