Display Panel Gate Fan-Out Line Routing for Narrow Borders
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Solution Overview
Problem
In large-sized, high-resolution display panels, the presence of gate fan-out lines affects the aperture ratio and response time due to their routing on different metal layers, making it challenging to achieve narrow borders and seamless splicing.
Innovation Solution
The display panel design features gate lines laterally on a substrate with gate fan-out lines insulated from them, forming sub-pixel units at intersections, where each gate fan-out line is connected to a gate line via a via hole, reducing the number of fan-out lines and improving connectivity with GOA driving units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If gate fan-out lines are routed on a side of data lines in standard definition pixel design, then the output signal of GOA can be connected to gate of thin film transistor, but the aperture ratio and response time of the panel are affected
Solution Approach 1:
The patent changes the routing dimension of gate fan-out lines from lateral routing on the same layer as data lines to longitudinal routing perpendicular to gate lines. This dimensional change allows fan-out lines to pass through intersections without conflicting with data lines, thereby increasing the aperture ratio while maintaining connectivity functionality.
Solution Approach 2:
The patent segments the gate control signal distribution by using multiple gate fan-out lines that branch from a single gate line at different positions. Each fan-out line serves a specific region, allowing independent optimization of signal routing paths and reducing interference with data lines in the aperture area.
2Reliability
If multiple gate fan-out lines are used to connect GOA output to gates, then the connectivity is improved, but the number of lines increases affecting the pixel structure
Solution Approach 1:
The gate fan-out lines serve multiple functions: they distribute control signals from GOA to multiple gate lines, provide structural support as part of the pixel architecture, and define region boundaries. This multi-functionality reduces the need for separate dedicated connection structures, thereby reducing overall device complexity while maintaining reliable connectivity.
3Measurement precision
If gate lines are designed on horizontal side for high resolution, then the resolution is improved, but the space required becomes larger making narrow border difficult
Solution Approach 1:
The patent employs asymmetric routing where gate lines are positioned horizontally for high-resolution pixel addressing, while gate fan-out lines are routed vertically through intersections. This asymmetric arrangement optimizes the horizontal resolution while minimizing the vertical peripheral space required for signal distribution, enabling narrow borders.
Data Source
AI summary
The present invention provides a display panel, and by means of using a plurality of sub-pixels as a sub-pixel unit, each sub-pixel unit corresponds to one gate fan-out line, such that a number of the gate fan-out lines of a pixel unit can be reduced, a width of a pixel opening area can be increased, and an aperture ratio (AR %) and response time (TR %) of the panel can be improved.