Display Panel Gate Timing for Variable-Frequency Power Reduction

The patent changes the frequency parameter of gate signals by differentiating between data writing gate signal frequency and data initialization/compensation gate signal frequency. Specifically, the data initialization gate signal frequency is set to half of the data writing gate signal frequency, and the compensation gate signal frequency is set to one-third of the data writing gate signal frequency. This parameter differentiation reduces power consumption while maintaining proper timing synchronization for display operations.

The patent implements dynamic frequency adjustment where the frequencies of data initialization and compensation gate signals adapt to the data writing gate signal frequency. When the data writing gate signal frequency is reduced, the data initialization gate signal frequency is reduced to half of the new data writing frequency, and the compensation gate signal frequency is reduced to one-third of the new data writing frequency. This dynamic adaptation maintains proper timing relationships across different operating frequencies.