Display Panel GOA and DEMUX Circuit for Narrow Lower Frame

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Solution Overview

Problem

Current DEMUX circuit designs in display panels struggle to further narrow lower frames while improving display resolutions, limiting the achievement of narrower frame designs.

Innovation Solution

The implementation of a display panel with cascading gate driver on array units, DEMUX switching units, and a DEMUX control signal generating circuit, which includes thin film transistors and branched control signal lines, allows for a horizontal sub-pixel arrangement and dot inversion driving mode, reducing frame space by integrating GOA units and DEMUX control signal generating circuits into a single drive chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If DEMUX circuit design is used to reduce data lines, then device complexity is reduced, but lower frame width cannot be further narrowed

Engineering Contradiction:
Improvenumber of data linesVSAvoidlower frame width
Core Design Contradiction:
Device complexityVSLength of stationary object

Solution Approach 1:

The patent changes the arrangement dimension of sub-pixels from traditional vertical stacking to horizontal arrangement. By arranging first, second, and third sub-pixels horizontally along the data line direction, the design transforms the spatial dimension utilization, allowing the lower frame to be shared across multiple sub-pixel rows and thereby reducing the lower frame width while maintaining signal multiplexing functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent inverts the traditional sub-pixel arrangement logic by placing sub-pixels of the same color (first, second, third sub-pixels) horizontally adjacent to each other rather than vertically stacked. This inversion of the arrangement paradigm enables the lower frame to serve multiple horizontal rows simultaneously, reducing the required lower frame width while preserving the DEMUX functionality.

Inventive Principle:
Principle #13The other way round (Inversion)

2Length of stationary object

If horizontal sub-pixel arrangement is implemented, then lower frame space is reduced, but display quality must be maintained

Engineering Contradiction:
Improvelower frame widthVSAvoiddisplay quality
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The patent implements dot inversion driving mode where adjacent sub-pixels with the same color are driven with alternating polarities. This periodic action compensates for the effects of reduced lower frame width by periodically inverting the driving polarity to maintain uniform display quality across the screen, preventing image sticking and ensuring reliable display performance despite the compact horizontal arrangement.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent changes the driving parameters by implementing dot inversion mode with alternating polarities for adjacent sub-pixels. This parameter change compensates for the reduced lower frame width effects and maintains display quality by dynamically adjusting the driving polarity to prevent image artifacts and ensure uniform visual performance across all horizontally arranged sub-pixels.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11705043B2Display panel
Publication Date: 2023.07.18 WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
  • US11705043B2 patent drawing
  • US11705043B2 patent drawing
  • US11705043B2 patent drawing

AI summary

A display panel includes an array substrate, a plurality of cascading GOA units, a plurality of DEMUX switching units, and a DEMUX control signal generating circuit. One DEMUX switching unit includes a scanning signal input port, at least two control signal input ports, and at least two scanning signal output ports. One GOA unit is connected to the scanning signal input port, the DEMUX control signal generating circuit is connected to the at least two control signal input ports, and the scanning signal output ports are connected to corresponding gate lines.