Display Panel Transistor Layout for High-PPI Pixel Circuits
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Solution Overview
Problem
Current display panels face challenges in achieving high pixel density (PPI) and desirable display effects, necessitating the development of a display panel with improved PPI and display quality.
Innovation Solution
The display panel incorporates a base substrate with a first transistor and a second transistor, where the first transistor has a silicon active layer and the second transistor has an oxide semiconductor active layer. The transistors are designed with specific dimensions and areas to optimize their performance and integration within the pixel circuit and drive circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the display pixel density is increased to improve display quality, then the PPI value increases, but the transistor area and circuit layout complexity increase
Solution Approach 1:
The patent applies parameter changes by utilizing transistors with different channel widths (W1 and W2) and different area relationships (S1<S2 or S1=S2) to optimize the pixel circuit performance. By adjusting the physical dimensions and material composition of transistors, the circuit achieves improved switching characteristics and signal control, enabling higher display quality without proportionally increasing circuit complexity
Solution Approach 2:
The patent employs composite materials by combining silicon-based transistors and oxide semiconductor transistors within the same pixel circuit. This hybrid approach leverages the high mobility of silicon transistors for drive functions and the low leakage characteristics of oxide semiconductor transistors for switch functions, achieving superior circuit performance that enables higher PPI displays with controlled complexity
2Ease of operation
If different transistor types are used to optimize circuit performance, then the switching characteristics improve, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies local quality by assigning different transistor types to specific circuit locations based on functional requirements. Silicon transistors with superior switching speed are positioned in drive transistor roles, while oxide semiconductor transistors with excellent off-state characteristics are placed in switch transistor roles. This localized optimization achieves superior overall circuit performance while maintaining a structured manufacturing approach
3Measurement precision
If the transistor area is reduced to increase pixel density, then the PPI increases, but the transistor performance and stability may deteriorate
Solution Approach 1:
The patent utilizes parameter changes by optimizing the channel width (W) and area (S) relationships of different transistor types to achieve area-efficient designs. By carefully selecting W1/W2 ratios and S1/S2 relationships, the circuit maintains adequate transistor performance metrics (such as on-current and threshold voltage stability) while minimizing the total area occupied by transistor structures, thereby enabling higher pixel density without sacrificing reliability
Data Source
AI summary
A display panel includes a base substrate, a first transistor, and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. A length of a channel region of the second transistor is L2. Along the direction perpendicular to the base substrate, a distance between the second gate electrode and the second active layer is D2.