Display Panel Insulating Film Thickness Segmentation
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Solution Overview
Problem
The increase in thickness of the insulating layer in display panels leads to a corresponding increase in the gate dielectric layer thickness, reducing the performance of the drive transistor and the overall display panel, while also increasing power consumption and reducing the lifetime due to increased parasitic capacitance.
Innovation Solution
A display panel design with sub-pixels featuring a gate dielectric layer, a first insulating layer, and a second insulating layer of different thicknesses, integrally formed through a halftone masking or grayscale masking process, where the gate dielectric layer is thinner than the first insulating layer, reducing parasitic capacitance and maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the thickness of the insulating layer between the data line and the scan line is increased to reduce parasitic capacitance, then the parasitic capacitance is reduced, but the thickness of the gate dielectric layer also increases, reducing the performance of the drive transistor
Solution Approach 1:
The patent divides the insulating layer into two separate layers: a first insulating layer between the data line and scan line (with greater thickness to reduce parasitic capacitance), and a second insulating layer between the data line and common line (with smaller thickness). This segmentation allows each layer to have optimized thickness for its specific function, resolving the contradiction between reducing parasitic capacitance and maintaining drive transistor performance.
Solution Approach 2:
The patent applies different thickness specifications to different regions of the insulating structure. The first insulating layer has a greater thickness specifically where needed to reduce parasitic capacitance between data and scan lines, while the second insulating layer has a smaller thickness where it serves a different function. This local differentiation of quality allows optimization for specific functional requirements without compromising overall performance.
2Object-affected harmful factors
If the thickness of the insulating layer is increased to reduce parasitic capacitance, then the parasitic capacitance is reduced, but the overall load and power consumption of the display panel increase
Solution Approach 1:
By segmenting the insulating layer into two layers with different thicknesses, the patent reduces parasitic capacitance more effectively than a uniform thickness design. The first insulating layer with greater thickness specifically targets the parasitic capacitance between data and scan lines, achieving better capacitance reduction without the excessive power consumption associated with uniformly increasing all insulating layer thicknesses.
3Ease of manufacture
If the gate dielectric layer thickness is increased to save manufacturing processes, then the manufacturing complexity is reduced, but the drive transistor performance deteriorates
Solution Approach 1:
The patent segments the insulating structure into two layers formed in one step, allowing different thicknesses for different functions. This maintains manufacturing simplicity while enabling the gate dielectric layer to have optimal thickness for drive transistor performance, rather than being constrained by a uniform thickness requirement.
Solution Approach 2:
The patent applies local quality by specifying different thicknesses for the first and second insulating layers. The gate dielectric layer can maintain its optimal thin thickness for high-performance transistor operation, while the first insulating layer provides greater thickness where needed for capacitance reduction, all achieved through a single manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall load on the display panel, improves the drive transistor's performance, and increases the resolution and response speed without increasing manufacturing complexity or costs, thereby enhancing the display panel's performance and longevity.
Implementation Method 1
a first insulating film pattern is deposited on a substrate of the display panel through a halftone masking or grayscale masking process
Data Source
AI summary
A display panel and a method for manufacturing the display panel are provided. The display panel includes a plurality of sub-pixels disposed on a substrate of the display panel. Each of the sub-pixels includes a drive transistor including a gate dielectric layer; a storage capacitor including a capacitance dielectric layer; a first insulating layer disposed between a data line of the display panel and a scan line of the display panel; a second insulating layer disposed between the data line and a common line of the display panel. The gate dielectric layer, the first insulating layer, the capacitance dielectric layer, and the second insulating layer are insulating films with different thicknesses integrally formed through a halftone masking or grayscale masking process, and a thickness of the gate dielectric layer is smaller than a thickness of the first insulating layer.