Display Panel Interval Pixel Layout for Brightness Uniformity

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Solution Overview

Problem

The brightness uniformity of display panels is compromised due to the integration of photosensitive elements, leading to non-uniform display brightness across different regions, particularly in full-screen solutions where the photosensitive element integration region has lower brightness compared to other display regions.

Innovation Solution

A display panel design with specific pixel circuit and light-emitting element arrangements, including a fourth display region with spaced pixel circuits to accommodate data lines, reducing overlapping and load differences, and optimizing wiring to ensure uniform brightness across regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the first display region is reused as a photosensitive element integration region, then the screen-to-body ratio is improved, but the display brightness uniformity deteriorates

Engineering Contradiction:
Improvescreen-to-body ratioVSAvoiddisplay brightness uniformity
Core Design Contradiction:
Area of stationary objectVSIllumination intensity

Solution Approach 1:

The patent applies local quality by creating different display regions with different characteristics: the first display region (photosensitive element integration region) has lower brightness, while the second display region has higher brightness. This intentional local differentiation allows the photosensitive elements to function properly while maintaining overall display quality through compensatory mechanisms in adjacent regions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces asymmetry by adding the fourth display region with pixel circuits arranged in a non-uniform pattern (including interval spaces) that differs from traditional uniform pixel arrangements. This asymmetric design allows data lines to pass through interval spaces, reducing interference and improving brightness uniformity across the display panel.

Inventive Principle:
Principle #4Asymmetry

2Manufacturing precision

If pixel circuits are densely arranged to increase display resolution, then the manufacturing precision is improved, but the wiring complexity increases

Engineering Contradiction:
Improvepixel circuit arrangement precisionVSAvoidwiring complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The fourth display region is segmented into multiple rows of pixel circuits with interval spaces between them. This segmentation allows data lines to pass through the interval spaces, reducing wiring complexity and interference while maintaining high pixel density in the display regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent resolves wiring conflicts by utilizing the spatial dimension of interval spaces within the pixel circuit arrangement. Instead of routing data lines through densely packed pixel circuits, the design allows lines to pass through the interval spaces, effectively using the available spatial dimension to reduce wiring complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12567349B2Display panel and display apparatus
Publication Date: 2026.03.03 WUHAN TIANMA MICRO ELECTRONICS CO LTD
  • US12567349B2 patent drawing
  • US12567349B2 patent drawing
  • US12567349B2 patent drawing

AI summary

A display panel and a display apparatus are provided. The display panel has first to fourth display regions, and includes first to fourth pixel circuits, first to fourth light-emitting elements, and first data lines. Each row of the fourth pixel circuits includes at least one first arrangement unit arranged along a first direction. Each first arrangement unit includes N fourth pixel circuits and a first interval space, where N is a positive integer. The N fourth pixel circuits are sequentially arranged adjacent to each other along the first direction, and the first interval space is located at a side of the N fourth pixel circuits along the first direction. At least one first data line passes through the first interval space.