Display Panel Fabrication Using Lift-Off Process for Self-Aligned TFTs
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Solution Overview
Problem
The manufacturing process of liquid crystal display panels is complex and costly, particularly due to issues with uniformity in poly silicon thin film transistors on large substrates, which limits their application to small size devices, and amorphous silicon transistors fail to meet high performance requirements.
Innovation Solution
A method for fabricating display panels that simplifies the manufacturing process by using a lift-off process to define patterns of the gate insulation layer, first passivation layer, and second patterned conductive layer simultaneously, eliminating the need for multiple photomasks and allowing self-alignment and short channel formation, thereby enhancing the aperture ratio and unifying thin film transistor unit characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If poly silicon thin film transistor units are used, then electrical mobility is improved, but manufacturing uniformity deteriorates due to crystallization processes on large substrates
Solution Approach 1:
The patent changes the material parameter from poly silicon to oxide semiconductor material, which has different crystallization characteristics. This parameter change allows achieving high electrical mobility (comparable to poly silicon) while avoiding the uniformity issues associated with poly silicon crystallization processes on large substrates, as oxide semiconductors can be processed with different thermal treatment conditions
2Manufacturing precision
If multiple photomasks are used for defining patterns, then pattern definition precision is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges multiple photomask steps into a single photomask step. The first photomask simultaneously defines the gate electrode pattern, gate insulation layer pattern, and first passivation layer pattern, eliminating the need for separate photomasks for each layer and thereby reducing manufacturing complexity while maintaining pattern definition precision
Solution Approach 2:
The patent introduces a patterned photoresist layer as an intermediary that enables single-step pattern definition. This photoresist layer serves as a common template for forming multiple patterns (gate electrode, gate insulation layer, first passivation layer) simultaneously, acting as a mediator that coordinates the formation of multiple layers in one exposure step
3Manufacturing precision
If conventional multi-step processes are used, then pattern accuracy is improved, but manufacturing time and cost increase
Solution Approach 1:
The patent performs preliminary pattern definition by forming a patterned photoresist layer that pre-establishes the geometric templates for multiple layers. This preliminary action allows subsequent layers (gate electrode, gate insulation layer, first passivation layer) to be formed simultaneously with accurate alignment, eliminating the need for multiple sequential exposure and development steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, simplifies the process, and improves the performance of thin film transistors by enhancing the aperture ratio and unifying unit characteristics, making it suitable for high-performance display devices.
Implementation Method 1
A lift-off process is performed for removing the patterned photoresist layer and the conductive layer on the patterned photoresist layer and forming a second patterned conductive layer
Implementation Method 2
An ashing process is performed for removing the second photoresist pattern and partially exposing an upper surface of the first passivation layer
Data Source
AI summary
A method for fabricating a display panel includes forming a first patterned conductive layer, a gate insulation layer, a semiconductor channel layer, a first passivation layer, a second patterned conductive layer and a pixel electrode on a first substrate. The first patterned conductive layer includes a gate electrode, and the second patterned conductive layer includes a source electrode, a drain electrode and a data line. The patterns of the gate insulation layer, the first passivation layer and the second patterned conductive layer are defined by an etching process and a lift-off process with the same photomask.