Display Panel Shared Electrode Layout to Reduce Line Crossings
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional LCD panels face issues with low circuit stability, inferior product yield, and high testing difficulty due to particle and electrostatic effects at the crossings of gate lines and shared common electrode lines.
Innovation Solution
The display panel design integrates the main trunks and branches of the shared common electrode lines, directly connecting thin-film transistors to the main trunks, reducing the number of branches and crossings between shared common electrode lines and gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate lines and shared common electrode lines are arranged in a conventional grid pattern, then the circuit can drive all sub-pixels, but the number of crossings increases leading to particle effects and electrostatic effects that reduce circuit stability
Solution Approach 1:
The patent merges multiple shared common electrode lines into a single shared line that serves multiple sub-pixels. Instead of having separate S_Com lines for each sub-pixel, one S_Com line is shared among multiple sub-pixels, reducing the total number of line crossings while maintaining the ability to drive all sub-pixels effectively
Solution Approach 2:
The patent changes the spatial arrangement of circuit lines by extending the shared common electrode line beyond the pixel array boundaries and routing it through dedicated regions. This dimensional reorganization reduces intersections with gate lines by changing the topological layout of the circuit connections
2Reliability
If the number of shared common electrode line branches is reduced, then circuit stability improves, but the complexity of ensuring proper electrical connection to all sub-pixels increases
Solution Approach 1:
The patent introduces an extension region as an intermediary structure that facilitates the connection between the reduced number of shared common electrode lines and multiple sub-pixels. This extension region acts as a mediator that simplifies the manufacturing process by providing a dedicated area for making electrical connections without increasing the number of main line branches
Solution Approach 2:
The patent segments the pixel array into multiple regions, each served by a dedicated shared common electrode line extension. This segmentation allows each extension to be independently connected to sub-pixels in its region, simplifying the manufacturing process while maintaining overall circuit stability
3Productivity
If shared common electrode lines cross gate lines frequently, then all sub-pixels can be driven, but particle effects and electrostatic effects cause short circuits and reduce yield
Solution Approach 1:
By merging multiple shared common electrode lines into fewer shared lines, the patent directly reduces the number of crossing points with gate lines. This reduction in crossings minimizes the locations where particle effects and electrostatic effects can occur, thereby reducing short circuits and improving production yield
4Reliability
If the shared common electrode line structure is simplified, then circuit stability improves, but the difficulty of detecting defective parts through test equipment increases
Solution Approach 1:
The extension region serves as an accessible intermediary structure that facilitates testing. By providing extended connection points that are more accessible to test equipment, the patent enables easier detection of defective parts while maintaining the simplified line structure that improves circuit stability
Data Source
AI summary
The present invention provides a display panel and a display device. The display panel includes a substrate, sub-pixels, and shared common electrode lines. The sub-pixels are arranged in an array on the substrate, and each sub-pixel includes thin-film transistors. The shared common electrode lines are arranged at intervals on the substrate, and electrically connected to the thin-film transistors. An orthographic projection of each shared common electrode line on the substrate partially overlaps with an orthographic projection of a thin-film transistor on the substrate.