Display Panel Clock-Line Load Adjustment for Uniform Scan Edges
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Solution Overview
Problem
Existing display technologies face issues with inconsistent load distribution among clock signal lines, leading to variations in falling edges of scan signals, which result in display defects such as horizontal stripes, particularly in large-size panels.
Innovation Solution
Incorporating load adjusting portions in connecting lines between the gate drive circuit and clock signal lines to compensate for load differences, ensuring consistent resistance and overlapping these portions with the clock signal lines to maintain uniform signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If connecting lines are extended to reach distant clock signal lines, then signal coverage is improved, but line resistance increases causing inconsistent falling edges
Solution Approach 1:
The patent applies local quality by differentiating the structure of connecting lines based on their position. Connecting lines are divided into first connecting lines (closer to gate drive circuit) and second connecting lines (farther from gate drive circuit). The second connecting lines include load adjusting portions while the first connecting lines do not, creating localized structural differences to compensate for position-dependent resistance variations.
Solution Approach 2:
The patent changes the electrical parameters of connecting lines by introducing load adjusting portions with specific resistance values. These load adjusting portions are designed with resistance values that compensate for the increased line resistance in second connecting lines, thereby equalizing the total resistance (line resistance + load adjusting portion resistance) across all connecting lines and achieving consistent signal falling edges.
2Reliability
If load adjusting portions are added to connecting lines, then signal consistency is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by differentiating the structure of connecting lines based on their position. Connecting lines are divided into first connecting lines (closer to gate drive circuit) and second connecting lines (farther from gate drive circuit). The second connecting lines include load adjusting portions while the first connecting lines do not, creating localized structural differences to compensate for position-dependent resistance variations.
Solution Approach 2:
The load adjusting portions serve multiple functions: they compensate for line resistance, equalize signal falling edges, and can be integrated with existing clock signal line structures. This multi-functionality reduces the need for additional separate compensation circuits, thereby limiting the increase in device complexity.
3Area of stationary object
If load adjusting portions are overlapped with clock signal lines, then trace space is minimized, but interference between lines increases
Solution Approach 1:
The patent applies the nested doll principle by placing the load adjusting portions within the spatial footprint of the clock signal lines. The load adjusting portions are positioned to overlap with the orthographic projections of clock signal lines on the base substrate, allowing one structure to occupy the same space as another without requiring additional lateral space.
Solution Approach 2:
The patent resolves the interference concern by utilizing the vertical dimension (z-direction) for overlapping structures. The load adjusting portions and clock signal lines are arranged in different layers or at different heights, allowing their orthographic projections to overlap on the base substrate while physically being separated in the vertical dimension, thus minimizing electromagnetic interference.
Data Source
AI summary
Disclosed is a display panel including a base substrate (101), and a gate drive circuit (40), a plurality of clock signal lines, and a plurality of connecting lines (51) that are disposed on the base substrate (101). The plurality of clock signal lines are located on a side of the gate drive circuit (40) along a first direction (X) and are arranged in sequence. Each connecting line (51) is electrically connected with the gate drive circuit (40) and a clock signal line. At least one connecting line (51) includes a load adjusting portion (512) configured to compensate for a load difference between different clock signal lines. An orthographic projection of the load adjusting portion (512) of the at least one connecting line (51) on the base substrate (101) is at least partially overlapped with an orthographic projection of at least one clock signal line on the base substrate (101).