Display Panel Signal-Line Layout for Narrow-Bezel LOT Circuits
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Solution Overview
Problem
Small-sized display devices face challenges in accommodating a light on test (LOT) circuit due to limited circuit placement space in the horizontal direction, preventing the achievement of a narrow bezel design.
Innovation Solution
The display panel incorporates a peripheral region with signal lines that include turning portions and transistors, allowing for efficient placement of transistors in two groups on opposite sides of the signal lines, reducing circuit placement space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the display panel size is increased to accommodate the LOT circuit, then the circuit placement space is sufficient, but the bezel width increases and the compact design is compromised
Solution Approach 1:
The signal line is configured to extend in the first direction (horizontal) and then turn to extend in the second direction (vertical) through a turning portion disposed in the peripheral region. This dimensional change in the signal line path allows the LOT circuit to be placed in the peripheral region without increasing the display panel size, thus maintaining narrow bezel width while providing sufficient circuit placement space.
2Device complexity
If transistors are disposed in a conventional linear arrangement, then the circuit layout is simple, but the peripheral region space is insufficient
Solution Approach 1:
The transistors are divided into two groups: a first group disposed on one side of the signal line and a second group disposed on the other side. This segmentation allows efficient utilization of the peripheral region space on both sides of the turning portion, increasing the available circuit placement area while maintaining a relatively simple overall layout structure.
Data Source
AI summary
A panel is provided. The display panel includes a plurality of signal lines and a plurality of transistors. The plurality of transistors are disposed in the peripheral region. Each of the plurality of transistors comprises a gate, a source and a drain. At least one of the plurality of signal lines is electrically connected to the source or the drain of one of the plurality of transistors. The at least one of the plurality of signal lines includes a turning portion. The turning portion is disposed in the peripheral region. Therefore, the panel of the disclosure can reduce the circuit placement space in the peripheral region.