Display Panel Wiring Layout for Low-Capacitance Lighting Tests
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional display panel wiring designs result in parasitic capacitance between data signal lines and test signal lines, leading to a color mixture phenomenon during lighting tests, where incorrect sub-pixels are activated, causing issues like color mixture and uneven displays.
Innovation Solution
The display panel design includes a substrate with separate conductive layers for test signal lines and data lines, where the projections of data lines on the test signal lines have reduced overlap areas, and notches are defined in the overlap regions to minimize capacitance, along with an insulative first and passivation layer to further reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data lines and test signal lines are routed in conventional wiring design with overlap regions, then the lighting test can be performed, but parasitic capacitance is generated causing color mixture phenomenon on screen images
Solution Approach 1:
The patent applies dimensional separation by routing data lines and test signal lines in different conductive layers (first conductive layer for test signal lines, second conductive layer for data lines). This vertical layering reduces parasitic capacitance while maintaining both lighting test functionality and display quality. The projection of data lines on the first conductive layer plane has reduced overlap with test signal lines, further minimizing capacitance coupling.
2Object-generated harmful factors
If voltage of data lines is lowered to prevent color mixture, then parasitic capacitance effect is reduced, but charge rate becomes overly low causing split screen images or uneven display
Solution Approach 1:
The patent segments the wiring into separate conductive layers for test signal lines and data lines. This physical separation reduces parasitic capacitance coupling, allowing data lines to operate at appropriate voltages without causing color mixture. The segmentation maintains both fast charge rates for accurate pixel activation and prevents harmful capacitive coupling effects.
3Object-generated harmful factors
If width of test signal lines is reduced in overlap regions, then parasitic capacitance is reduced, but signal integrity may be compromised
Solution Approach 1:
The patent applies local quality by varying the width of test signal lines based on location. In overlap regions where parasitic capacitance would be generated, the test signal line width is reduced. In non-overlap regions, the full width is maintained to ensure signal integrity. This localized adjustment optimizes both capacitance reduction and signal quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces parasitic capacitance between data lines and test signal lines, preventing color mixture and ensuring accurate pixel activation during lighting tests, while maintaining display quality by minimizing the relative area of overlap and using insulative materials to enhance insulation.
Implementation Method 1
a first insulative layer disposed between the first conductive layer and the second conductive layer; and a passivation layer disposed between the first insulative layer and covering the second conductive layer
Data Source
AI summary
The present application provides a display panel including a first conductive layer, a second conductive layer, and a third conductive layer. The present application reduces an overlap area between test signal lines and data lines to further reduce a capacitance therebetween to prevent an issue of color mixture of a screen image during a lighting test.