Display Panel Pixel Circuit with P-Type LTPS for Leakage Control
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Solution Overview
Problem
Display panels using low temperature polycrystalline oxide (LTPO) technology face issues with leakage current in driving transistors due to voltage changes on gate lines affecting normal operation.
Innovation Solution
A display panel design incorporating P-type low temperature polysilicon transistors with a novel pixel driving circuit configuration, including specific layer arrangements and conductive layers to stabilize gate voltages and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If N-type oxide transistor is used in pixel driving circuit, then leakage current is reduced, but gate line voltage changes adversely affect normal drive
Solution Approach 1:
The patent changes the transistor type from N-type oxide to P-type low temperature polysilicon, fundamentally altering the electrical parameters and characteristics of the pixel driving circuit to eliminate sensitivity to gate line voltage changes while maintaining low leakage current performance
Solution Approach 2:
The P-type low temperature polysilicon transistor serves multiple functions: it provides low leakage current during the light-emitting stage, maintains stable operation against gate line voltage fluctuations, and enables simplified circuit design without requiring separate gate lines for oxide transistors
2Ease of operation
If separate gate line is provided for oxide transistor, then gate driving signal is supplied, but device complexity increases
Solution Approach 1:
The patent merges the gate line functions by using a single gate line that serves both the second transistor and the driving transistor, eliminating the need for separate gate lines and reducing overall circuit complexity while maintaining proper gate driving signal supply
Data Source
AI summary
A display panel includes a base substrate, a second conductive portion, and first, second and fourth conductive layers located at a side of the base substrate. The first conductive layer includes a first gate line of which orthographic projection extends along a first direction and a partial structure forms a fourth transistor's gate and a first conductive portion forming a driving transistor's gate. The second conductive layer includes a second gate line of which orthographic projection extends along the first direction and is located between orthographic projections of the first conductive portion and the first gate line, and a partial structure forms a second transistor's first gate. Orthographic projection of the second conductive portion at least partially overlaps with that of the first gate line. The fourth conductive layer includes a first connection portion connected to the first and second conductive portions through a via hole.