Multi-bit Memory Pixel Circuit for Display Panel Gray Level Control

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Solution Overview

Problem

Conventional memory in pixel (MIP) circuits typically use one-bit data storage, limiting color depth to two levels (black or white), and while intermediate gray levels can be generated through pixel rendering or dithering, this reduces resolution.

Innovation Solution

A display panel with a multi-bit memory pixel array that includes image data storage capacitors and refresh units, allowing for increased gray levels by selectively controlling voltage through shunt and refresh units, enabling the storage and refresh of different image data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If one-bit data storage is used in MIP circuits, then device complexity is reduced, but color depth is limited to two levels (black or white)

Engineering Contradiction:
Improvememory structure complexityVSAvoidcolor depth
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The pixel circuit is divided into multiple functional units: a storage capacitor for holding data, a sample unit for capturing voltage levels, a capacitive element for storing sampled data, and refresh units for maintaining data integrity. This segmentation enables multi-bit storage capability while keeping each component simple and manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from one-bit storage to multi-bit storage by utilizing voltage levels across multiple gray scales. The capacitive element can store different voltage levels corresponding to multiple gray levels, effectively adding a dimension to data representation without proportionally increasing circuit complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If pixel rendering or dithering is used to generate intermediate gray levels, then color depth is improved, but resolution is reduced

Engineering Contradiction:
Improvecolor depthVSAvoidimage resolution
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The sample unit creates a copy of the voltage level from the pixel electrode and stores it in the capacitive element. This copied voltage level can then be used to represent gray levels without requiring additional pixels or reducing the original pixel array resolution, thus maintaining image quality while achieving multi-level gray representation.

Inventive Principle:
Principle #26Copying

3Quantity of substance

If multi-bit memory is implemented in pixel elements, then color depth and gray levels are increased, but device complexity increases

Engineering Contradiction:
Improvenumber of gray levelsVSAvoidpixel circuit complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The storage capacitor serves multiple functions: it stores image data, works with the sample unit to capture voltage levels, and cooperates with the capacitive element and refresh units to maintain and update multi-bit data. This multi-functionality reduces the need for separate dedicated components for each function, thereby limiting the increase in overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The refresh units automatically maintain the voltage levels in the capacitive element without requiring external intervention. The circuit self-regulates to preserve the multi-bit data stored in the capacitive element, reducing the need for complex external control mechanisms and minimizing the increase in device complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9208714B2Display panel for refreshing image data and operating method thereof
Publication Date: 2015.12.08 INNOLUX CORP
  • US9208714B2 patent drawing
  • US9208714B2 patent drawing
  • US9208714B2 patent drawing

AI summary

A display panel is provided, including an image data storage capacitor, a capacitive element, and four switches. The image data storage capacitor stores an image data. The sample unit has a control terminal for receiving a sample control signal. The capacitive element has a first terminal coupled to a pixel electrode of the image data storage capacitor via the sample unit. The first refresh unit has a control terminal coupled to the first terminal. The second refresh unit has a control terminal for receiving a refresh control signal. The third and first refresh units are serially coupled with each other between a corresponding source line and the image data storage capacitor for receiving a data signal. The shunt unit has a control terminal coupled to the pixel electrode, a data terminal coupled to the first terminal, and another data terminal for receiving a shunt control signal.