Display Panel Layout With Mixed TFTs and Fewer Mask Steps
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Solution Overview
Problem
Existing display panel manufacturing processes face challenges in achieving high speed and reliability while also reducing the number of masks used, which complicates the manufacturing process and increases costs.
Innovation Solution
The proposed solution involves a display panel design with a base layer having a first and second area, where the second area is bent from the first. An inorganic layer overlaps both areas, and thin-film transistors with silicon and oxide semiconductor patterns are disposed on this layer. The use of insulation layers and etching processes reduces the number of masks required in the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional display panel manufacturing processes are used, then manufacturing reliability is maintained, but the number of masks required increases process complexity and cost
Solution Approach 1:
The patent combines multiple mask functions into a single mask structure. The mask includes a first mask pattern for defining pixel electrodes and a second mask pattern for defining common electrodes, allowing both patterns to be formed simultaneously in one photolithography step rather than requiring separate masking operations.
Solution Approach 2:
The mask structure serves multiple functions: it defines both pixel electrode patterns and common electrode patterns, acts as a barrier layer, and provides structural support during the manufacturing process. This multi-functional design reduces the total number of masks needed in the manufacturing sequence.
2Manufacturing precision
If more masks are used in the manufacturing process, then manufacturing precision can be maintained, but the number of masks increases cost and process time
Solution Approach 1:
Multiple electrode pattern definitions are merged into a single mask structure, allowing simultaneous formation of pixel electrodes and common electrodes. This reduces the number of sequential photolithography steps while maintaining pattern precision through carefully designed mask features.
Solution Approach 2:
The mask is designed in advance with pre-defined patterns for both pixel and common electrodes, allowing both to be formed in one step. This preliminary design approach eliminates the need for multiple sequential masking operations and reduces overall manufacturing cycle time.
3Ease of manufacture
If the display panel structure is simplified to reduce manufacturing steps, then manufacturing cost decreases, but device reliability and performance may be compromised
Solution Approach 1:
The patent merges the formation of pixel electrodes and common electrodes into a single photolithography step using a multi-pattern mask. This simplification in the number of manufacturing steps does not compromise reliability because the mask is specifically designed to ensure proper alignment and electrical isolation between different electrode types.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the pixel electrodes and common electrodes formed by the same mask. This mediator ensures proper electrical isolation and prevents short circuits, maintaining device reliability while allowing the simplified single-step patterning approach.
Data Source
AI summary
A display panel includes a base layer including a first area and a second area. At least one inorganic layer disposed on the base layer overlaps the first area and the second area. The at least one inorganic layer comprises a lower opening. A first thin-film transistor is disposed on the at least one inorganic layer. The first thin-film transistor includes a silicon semiconductor pattern. A second thin-film transistor is disposed on the at least one inorganic layer. The second thin-film transistor includes an oxide semiconductor pattern. A plurality of insulation layers overlap the first area and the second area. An upper opening extends from the lower opening. A signal line is electrically connected to the second thin-film transistor. An organic layer is disposed in the lower opening and the upper opening. A light emitting element is disposed on the organic layer.