Display Panel Signal Line Isolation via Multi-Layer Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In display devices, particularly in industrial control display screens, the common signal line often overlaps with synchronization signal lines, leading to electrostatic breakdown and potential short circuits due to static electricity, which affects the display panel's performance and reliability.
Innovation Solution
The display panel design includes a base substrate with a display region and a peripheral region, featuring a common signal line that does not overlap with the first and second signal lines. Instead, these signal lines are electrically connected through a circuit board and third pads, ensuring that the common signal line is isolated from the synchronization signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the common signal line and synchronization signal lines are arranged close together to save space, then the device complexity is reduced, but electrostatic breakdown and short circuits occur due to static electricity
Solution Approach 1:
The patent transitions from a planar arrangement of signal lines to a three-dimensional layered structure. The common signal line is placed in a first metal layer while synchronization signal lines are placed in a second metal layer, utilizing the vertical dimension to separate signal lines that would otherwise overlap in the same plane. This dimensional change eliminates electrostatic breakdown risks while maintaining compact device layout.
Solution Approach 2:
The patent divides the signal line arrangement into distinct segments by separating the common signal line and synchronization signal lines into different metal layers. This segmentation isolates the signal lines electrically and spatially, preventing electrostatic interaction while maintaining the overall compactness of the display panel structure.
2Ease of manufacture
If the common signal line overlaps with synchronization signal lines to simplify the structure, then the manufacturing process is easier, but electrostatic discharge causes short circuits
Solution Approach 1:
The patent resolves the contradiction by moving to a multi-layer metal structure where the common signal line and synchronization signal lines are positioned in different vertical layers. This dimensional separation maintains the simplicity of the fabrication process while eliminating the harmful electrostatic discharge effect that occurs when lines overlap in the same plane.
Solution Approach 2:
The patent introduces intermediate metal layers as mediators between the common signal line and synchronization signal lines. These intermediate layers provide electrical isolation and spatial separation, preventing direct electrostatic interaction while allowing both signal lines to coexist in the overall structure without causing short circuits.
3Device complexity
If signal lines are arranged in the same layer to reduce manufacturing steps, then production is simpler, but electrostatic breakdown occurs between lines
Solution Approach 1:
The patent employs dimensional change by transitioning from a single-layer planar arrangement to a multi-layer three-dimensional structure. The common signal line is positioned in one metal layer while synchronization signal lines are positioned in another metal layer, utilizing the vertical dimension to achieve electrostatic isolation without significantly increasing overall device complexity.
Solution Approach 2:
The patent segments the signal line arrangement into distinct metal layers, separating the common signal line from synchronization signal lines. This segmentation provides electrical isolation and prevents electrostatic breakdown while maintaining a manageable structure that can be manufactured using standard multi-layer fabrication processes.
Data Source
AI summary
A display panel, a circuit board and a display device are provided. The display panel includes a first pad region including a first pad connected to a first integrated circuit, a second pad region including a second pad electrically connected to a second integrated circuit, a third pad region including third pads electrically connected to a circuit board and a common signal line electrically connected to the common electrode of the sub-pixel. The display panel further includes a first signal line and a second signal line, the first pad is electrically connected to the third pad through the first signal line, the second pad is electrically connected to the third pad through the second signal line; the first signal line and the second signal line are electrically connected to each other through the third pads and the circuit board.