Display Panel Multi-Row Pixel Circuits for Charging Uniformity
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Solution Overview
Problem
Display apparatuses suffer from poor display effects and display non-uniformity in secondary-screen areas due to large transition areas necessitating long connection lines between pixel circuits and sub-pixels, leading to parasitic capacitances and varying charging rates.
Innovation Solution
The display panel is designed with a first active area having a higher light transmittance than a second active area, featuring first pixel circuits arranged in at least two rows and fewer columns than the total number of sub-pixels, reducing wire lengths and parasitic capacitances, and ensuring consistent charging rates across sub-pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pixel circuits are arranged in a traditional layout to drive sub-pixels in the first active area, then the connection lines become long, but this leads to increased parasitic capacitances and varying charging rates causing display non-uniformity
Solution Approach 1:
The patent applies dimensionality change by arranging pixel circuits corresponding to sub-pixels in the same pixel unit across multiple rows rather than a single row. This spatial redistribution in the row dimension reduces the horizontal distance between pixel circuits and sub-pixels, thereby shortening connection lines and reducing parasitic capacitances while maintaining proper driving functionality
Solution Approach 2:
The patent segments the arrangement of pixel circuits by dividing them into multiple row groups, where each group corresponds to a subset of sub-pixels in a pixel unit. This segmentation allows optimization of connection line lengths for different sub-pixel groups independently, reducing overall parasitic capacitance and improving charging uniformity across the display
2Reliability
If the number of columns of pixel circuits equals the total number of sub-pixels, then each sub-pixel can be driven independently, but this increases wire lengths and parasitic capacitances
Solution Approach 1:
The patent introduces a multi-row arrangement structure where pixel circuits are distributed across at least two rows. This dimensional change in the arrangement structure allows reduction of connection line lengths without compromising the one-to-one correspondence between pixel circuits and sub-pixels, thereby maintaining charging rate consistency while reducing parasitic effects
Solution Approach 2:
The patent applies local quality by making the number of columns of pixel circuits less than the total number of sub-pixels in certain row regions. This local optimization allows reduction of wire lengths and parasitic capacitances in specific areas while maintaining overall display performance through the multi-row distribution strategy
Data Source
AI summary
Embodiments of the present application disclose a display panel and a display apparatus. A light transmittance of the first active area of the display panel is greater than a light transmittance of the second active area of the display panel. The display panel includes a plurality of first pixel units located in the first active area and a plurality of first pixel circuits located in the second active area. The first pixel unit includes a plurality of sub-pixels. The first pixel circuit is connected to the first electrode of the corresponding sub-pixel in the first pixel unit through a wire. The first pixel circuits are arranged in an array. The first pixel circuits corresponding to the plurality of sub-pixels in the same first pixel unit are arranged in at least two rows and in a number of columns less than a total number of sub-pixels in the first pixel unit.