Display Panel Multiplexing Layout for Narrow Bezels and High Refresh
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Solution Overview
Problem
Existing display technologies face challenges in increasing the screen-to-body ratio and reducing bezel size while maintaining a high refresh rate, particularly in display products with limited bezel space.
Innovation Solution
A display panel design that incorporates a multiplexing circuit with multiplexing transistors arranged in a specific array configuration, allowing for a 1:2 design that provides data signals to adjacent sub-pixels, reducing the occupied space and facilitating a high refresh rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional multiplexing circuit layout is used, then the circuit can provide data signals to sub-pixels, but the occupied space in the bezel region is large
Solution Approach 1:
The patent applies dimensionality change by arranging multiplexing transistors in a matrix configuration with row and column directions, and by utilizing multi-layer conductor structures. This spatial reorganization reduces the occupied area in the bezel region while maintaining the circuit's functionality for providing data signals to sub-pixels.
Solution Approach 2:
The multiplexing circuit is segmented into multiple multiplexing units, each handling specific data signal routing. The transistors are divided into rows and columns, allowing independent control and optimized space utilization. This segmentation enables the circuit to maintain complexity management while reducing overall bezel occupation.
2Productivity
If the refresh rate is increased, then display performance is improved, but the bezel space requirements increase
Solution Approach 1:
The patent merges multiple data signal paths into a unified multiplexing circuit architecture that operates efficiently in limited bezel space. By combining row and column control lines and utilizing shared conductor layers, the circuit achieves high refresh rate capability without proportionally increasing bezel occupation.
Solution Approach 2:
The patent utilizes three-dimensional conductor layer stacking to achieve high refresh rate performance in reduced two-dimensional bezel space. Multiple conductor layers are arranged vertically, allowing increased signal routing capacity and refresh rate capability without linearly increasing the horizontal and vertical footprint in the bezel region.
Data Source
AI summary
A display panel, comprising: a substrate (10), a plurality of sub-pixels (PX) and a plurality of data lines (DL) located in a display area (AA), and a multiplexing circuit (30) located in a first frame area (B1). The plurality of data lines (DL) are connected to the plurality of sub-pixels (PX). The multiplexing circuit (30) comprises a plurality of multiplexing units (31, 32, 33). At least one multiplexing unit (31, 32, 33) comprises a plurality of multiplexing transistors. The multiplexing transistors of the plurality of multiplexing units (31, 32, 33) are arranged in a plurality of rows and columns, one row of multiplexing transistors comprises a plurality of multiplexing transistors arranged in a first direction (X), and one column of multiplexing transistors comprises a plurality of multiplexing transistors arranged in a second direction (Y). The first direction (X) intersects with the second direction (Y).