Display Panel Data-Line Compensation for Vertical Mura Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display panels with narrow bezel or borderless designs face challenges in optimizing display performance due to vertical display non-uniformity, also known as the Mura phenomenon, caused by differences in data signal delays across different data lines.
Innovation Solution
The display panel incorporates a shift register with cascaded shift units divided into sub-units located alongside sub-pixels, connecting lines that overlap with data lines to generate parasitic capacitance, and compensation structures in a second display region that overlap with data lines to balance load and signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If data lines are extended to cover the entire display region including narrow bezel areas, then the display area is increased and borderless design is achieved, but signal delay differences and Mura phenomenon worsen
Solution Approach 1:
The patent applies local quality by dividing the display region into first and second display regions with different structural configurations. The first display region contains shift register units with connecting lines that overlap data lines, while the second display region contains compensation structures that also overlap data lines. This localized differentiation allows each region to address specific signal delay issues, thereby improving overall display uniformity across the extended display area including narrow bezel regions.
Solution Approach 2:
The patent changes physical parameters by creating overlapping structures between connecting lines and data lines in the first display region, and between compensation structures and data lines in the second display region. This overlapping generates parasitic capacitance that compensates for signal delay differences. By adjusting the overlap extent and positioning, the signal transmission characteristics are modified to reduce Mura phenomenon while maintaining the extended display area.
2Manufacturing precision
If shift register and connecting lines are placed in the first display region with overlapping configurations, then signal delay compensation is improved, but device complexity increases
Solution Approach 1:
The patent merges the shift register function with the data line connection function by placing connecting lines that overlap with data lines within the shift register units in the first display region. This integration allows the shift register to perform both signal shifting and signal delay compensation simultaneously. The compensation structures in the second display region are also merged with data lines through overlapping, enabling dual functionality without proportionally increasing device complexity.
3Manufacturing precision
If compensation structures are added in the second display region overlapping with data lines, then Mura phenomenon is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent addresses manufacturing complexity by transitioning to a multi-layer structure where compensation structures in the second display region overlap with data lines in the perpendicular direction (vertical dimension). This dimensional approach allows compensation structures to be formed in different layers rather than requiring complex lateral routing, simplifying the manufacturing process while achieving the desired signal delay compensation and display uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively balances the load of data lines, reduces vertical display non-uniformity, and enhances the display performance of display panels with ultra-narrow bezel or borderless designs.
Implementation Method 1
one of the first data lines overlaps with one of the connecting lines in a direction perpendicular to a plane of the display panel
Implementation Method 2
The compensation structures are located in the second display region, and each overlap with at least one of the second data lines in the direction perpendicular to the plane of the display panel
Data Source
AI summary
A display panel including a display region including first and second display regions, and sub-pixels in the display region, data lines electrically connected to the sub-pixels and including first data lines in the first display region and second data lines located in the second display region; a shift register in the first display region and including cascaded shift units, each shift unit being divided into at least two sub-units, and one sub-unit being located at a side of one sub-pixel connecting lines electrically connected to the sub-units of the shift units, one of the first data lines overlapping with one of the connecting lines in a direction perpendicular to a plane of the display panel; and compensation structures located in the second display region, and each overlapping with at least one of the second data lines in the direction.