Display Panel Dual-Sided Chip-On-Film Layout for Narrow Bezels
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Solution Overview
Problem
Large-size OLED display devices face challenges in achieving a narrow bezel design due to the spatial constraints of their structural components, which affect the visual effect.
Innovation Solution
A display panel design featuring a dual-sided chip-on-film configuration with centrosymmetric chip-on-films on opposite sides of the display region, combined with a groove in the planarization layer and frame sealant overlapping with wires, allows for efficient utilization of peripheral space and reduces bezel width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If traditional single-sided chip configuration is used, then manufacturing is simpler, but bezel width is larger
Solution Approach 1:
The patent divides the driving circuit configuration into two separate chip-on-film components positioned on opposite sides of the display region. This segmentation allows each chip to handle a portion of the display panel's driving functions, enabling the wires to be routed through the dummy pixel region more efficiently and reducing the required bezel width on each side while distributing the structural complexity across multiple components
Solution Approach 2:
The patent transitions from a single-sided chip configuration to a dual-sided configuration by utilizing the third dimension (depth/thickness) and opposite surfaces of the display panel. By placing chip-on-films on both the first and second sides of the substrate, the design creates a more balanced wire routing path through the dummy pixel region, reducing the horizontal space required for wiring and thereby narrowing the bezel width
2Area of stationary object
If chip-on-film is placed on both sides of display region, then wire routing space is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent employs asymmetric placement of chip-on-films on opposite sides of the display region, where each chip is positioned to optimize wire routing in its respective direction. The first chip-on-film on the first side and the second chip-on-film on the second side are arranged to create an asymmetric but balanced wire path through the dummy pixel region, maximizing space utilization while maintaining manufacturability through standardized mounting processes
Solution Approach 2:
The chip-on-films are pre-formed and prepared as separate components before being mounted onto the display panel substrate. This preliminary preparation allows for precise positioning and routing of wires through the dummy pixel region before final assembly, optimizing the peripheral space utilization while simplifying the overall manufacturing process by separating component fabrication from panel assembly
Data Source
AI summary
A display panel and a display device are provided, the display panel has a display region, a dummy pixel region and a circuit region, the display region includes a planarization layer and an encapsulation layer. The circuit region includes a plurality of wires and a frame sealant. The frame sealant overlaps with at least a part of the wires, the encapsulation layer overlaps with at least a part of the frame sealant. The planarization layer includes at least one groove in the circuit region, and overlapping with at least a part of the wires. A first side and a second side of the display region include a binding region, and at least one first chip-on-film in the first binding region on the first side and at least one second chip-on-film in the second binding region on the second side are centrosymmetric with respect to a center of the display region.