Display Panel Shift Register with Periodic Node Reset
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Solution Overview
Problem
Display devices experience display abnormalities due to output signal drift caused by unstable operation of the gate drive circuit, particularly in the maintenance stage after signal output.
Innovation Solution
A shift register unit design with inverted phase level signals and transistors configured to maintain stable node potentials through periodic resetting, using N-type transistors to control signal output and prevent current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate drive circuit outputs drive signals for pixels in a present row, then the display operation proceeds, but output signal drift occurs causing display abnormality
Solution Approach 1:
The patent applies periodic action by implementing a maintenance stage that periodically resets node potentials after signal output. The first control sub-circuit periodically transmits the first level signal to the first node based on clock signals during the maintenance stage, preventing signal drift through periodic reinforcement of stable potential states.
Solution Approach 2:
The patent implements feedback mechanisms where the first control sub-circuit monitors node potentials and actively corrects drift by transmitting level signals. The circuit uses the state of node N2 and clock signals to determine when to reset node N1, creating a feedback loop that maintains signal stability throughout the display operation cycle.
2Ease of operation
If transistors are used to control signal output, then signal transmission is achieved, but current leakage occurs causing unstable operation
Solution Approach 1:
The patent extracts and addresses the current leakage problem by separating the signal transmission function from the potential drift issue. The first control sub-circuit is specifically designed to counteract leakage effects by periodically resetting node potentials, effectively removing the harmful leakage influence from the system operation.
Solution Approach 2:
The patent changes the electrical parameters of the circuit by actively adjusting node potentials through the first control sub-circuit. By dynamically modifying the potential levels at node N1 based on clock signals and node N2 state, the circuit compensates for parameter drift caused by transistor leakage.
3Device complexity
If node potentials are not reset periodically, then circuit operation is simple, but potential drift occurs leading to display abnormalities
Solution Approach 1:
The patent applies preliminary action by preparing the first control sub-circuit in advance to reset node potentials before drift becomes problematic. The maintenance stage is built into the operation cycle, proactively preventing potential drift rather than reacting to it after display abnormalities occur.
Data Source
AI summary
A shift register unit is provided and includes an input circuit, which is connected to first and second signal input terminals and a first node and receives a first level signal, transmits signal of the first signal input terminal to the first node in response to signal of the first signal input terminal and first level signal to the first node in response to signal of the second signal input terminal; a first control sub-circuit connected to first and second nodes and a clock signal terminal and receiving first level signal, which transmits first level signal to the first node in response to signals of the second node and clock signal terminal; a first output sub-circuit connected to first node, clock signal terminal and signal output terminal, which transmits signal of the clock signal terminal to the signal output terminal in response to signal of the first node.