Display Panel Pixel Circuit Using Silicon and Oxide Transistors

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Solution Overview

Problem

Current display technologies face challenges in achieving high pixel density (PPI) and desirable display effects, particularly in mobile devices, where existing display panels struggle to optimize the combination of silicon and oxide semiconductor transistors for improved performance and space efficiency.

Innovation Solution

The display panel incorporates a combination of silicon and oxide semiconductor transistors with specific gate and active layer configurations, including multiple gate electrodes, to optimize channel region lengths and distances, ensuring high responsiveness and stability while minimizing circuit space, thereby enhancing pixel density and display quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the display pixel density is increased to improve display quality, then the PPI value increases and display fidelity improves, but the transistor area occupation increases and circuit layout becomes more complex

Engineering Contradiction:
Improvedisplay fidelityVSAvoidcircuit layout complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by using different semiconductor materials (silicon for first transistor, oxide semiconductor for second transistor) in different regions of the pixel circuit. This allows each transistor to be optimized for its specific function: the silicon transistor provides high-speed switching for the switch transistor role, while the oxide semiconductor transistor provides low leakage current for the drive transistor role, thereby achieving high PPI without compromising circuit performance

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the material parameter of the semiconductor layer to resolve the contradiction. By selecting silicon material for the first transistor and oxide semiconductor material for the second transistor, the patent achieves different electrical characteristics (mobility, leakage current) that allow compact circuit design at high PPI while maintaining proper transistor functionality

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the transistor channel width-to-length ratio is optimized to improve transistor performance, then the transistor area increases, but the available pixel area decreases

Engineering Contradiction:
Improvetransistor performanceVSAvoidpixel area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent optimizes transistor performance within limited area by assigning different material qualities to different transistors. The silicon-based first transistor achieves high mobility with smaller area, while the oxide semiconductor second transistor achieves ultra-low leakage with appropriate area, allowing the pixel circuit to meet performance requirements without excessive area occupation

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses composite material strategy by combining silicon material and oxide semiconductor material in the same pixel circuit. This composite approach allows the circuit to benefit from both material systems: silicon provides high-speed operation and oxide semiconductor provides low leakage, achieving superior overall performance in compact area

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS20240063228A1Display panel and display device
Publication Date: 2024.02.22 XIAMEN TIANMA MICRO ELECTRONICS
  • US20240063228A1 patent drawing
  • US20240063228A1 patent drawing
  • US20240063228A1 patent drawing

AI summary

A display panel includes a base substrate, a first transistor and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes an oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. The first transistor further includes a third gate electrode. Along the direction perpendicular to the base substrate, a distance between the third gate electrode and the first active layer is D3, and D1<D3.