Display Panel Non-Display Region Reduction via 3D Pad Integration
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Solution Overview
Problem
Existing display devices have a significant non-display region that reduces the effective area for image display, limiting the ability to minimize bezel width and enhance the display-to-total-area ratio.
Innovation Solution
A display panel design with a reduced non-display region is achieved by incorporating a base layer with defined regions, pixels, lines, pads, and a test circuit, where the pads are strategically positioned to minimize the area occupied by the test circuit and electrostatic discharge protection circuits, allowing for a more efficient layout that increases the display area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the test circuit and electrostatic discharge protection circuits are positioned in the conventional layout, then the circuits can be properly integrated, but the non-display region area increases, reducing the display-to-total-area ratio
Solution Approach 1:
The patent positions the pads in the third direction (depth dimension) rather than only in the planar layout, allowing the test circuit and electrostatic discharge protection circuits to be integrated vertically. This dimensional transition reduces the occupied area in the display plane while maintaining proper circuit functionality and protection capabilities.
Solution Approach 2:
The pads are nested within or adjacent to the pixel structures in the base layer, allowing the test circuit and electrostatic discharge protection circuits to share space with the display pixels. This nesting approach minimizes the overall non-display region area while ensuring proper electrical connections and protection functions.
2Productivity
If the bezel width is minimized to enhance display performance, then the display-to-total-area ratio increases, but the space for integrating test circuits and protection circuits is reduced
Solution Approach 1:
By transitioning from planar layout to three-dimensional positioning, the patent allows test circuits and protection circuits to be integrated within the vertical profile of the display device rather than requiring additional horizontal space. This enables minimal bezel width while maintaining necessary circuit integration capabilities.
Solution Approach 2:
The patent merges the functions of the test circuit, electrostatic discharge protection circuit, and display pixels into a compact integrated structure in the base layer. The pads serve multiple purposes: electrical connection, electrostatic discharge protection, and test circuit integration, reducing the overall device complexity despite the minimal bezel width.
Data Source
AI summary
A display panel includes a base layer including a first region, and a second region which is adjacent to the first region, a pixel disposed on the first region of the base layer, a line electrically connected to the pixel and extending from the first region to the second region, a pad electrically connected to the line, at which an electrical signal is input to the display panel from outside thereof and disposed under a top surface of the base layer, and a test circuit on the base layer, in the second region, the test circuit being spaced apart from the first region and further from the first region than the pad.