Display Panel Parallel Signal Lines Reduce RC Delay
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Solution Overview
Problem
Display panels with Gate driver On Array (GOA) configurations often experience abnormal color phenomena due to high resistance in driving signal lines, leading to prolonged rise and fall times and insufficient charging, causing purplish and bluish biases in the display area.
Innovation Solution
The implementation of a display panel design where first and second driving signal lines are electrically connected in parallel to the output terminals of gate drivers, reducing resistance-capacitance delay and enhancing driving capability, thereby preventing abnormal colors by improving the charging time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single driving signal line is used to connect the gate driver to the pixel driving circuits, then the device complexity is reduced, but the resistance increases causing prolonged rise and fall times and abnormal colors
Solution Approach 1:
The single driving signal line is segmented into multiple parallel signal lines (first driving signal line and second driving signal line) that collectively connect the gate driver output terminal to the pixel driving circuits. This segmentation reduces the resistance and capacitance of each individual line while maintaining the overall connection function, thereby reducing RC delay and preventing abnormal colors.
Solution Approach 2:
Multiple driving signal lines are merged in parallel between the gate driver output terminal and the pixel driving circuits. The first driving signal line and second driving signal line are arranged in different layers and both connect to the same output terminal, effectively combining their conductive paths to reduce overall resistance and improve signal transmission speed.
2Area of stationary object
If the driving signal line length is increased to cover the entire display area, then the coverage area is improved, but the resistance-capacitance delay increases causing insufficient charging
Solution Approach 1:
The patent transitions from a single-plane signal line arrangement to a multi-layer arrangement where the first driving signal line and second driving signal line are located in different layers. This dimensional change allows parallel signal paths without increasing the planar footprint, reducing RC delay while maintaining full display area coverage.
3Duration of action of moving object
If the gate driver output impedance is reduced to improve charging speed, then the charging time is reduced, but the resistance in the signal line remains high causing abnormal colors
Solution Approach 1:
Multiple signal lines are merged in parallel to reduce the equivalent resistance of the signal transmission path. By combining the first driving signal line and second driving signal line in parallel, the overall resistance is reduced without changing the gate driver output impedance, thereby preventing voltage drops and abnormal colors while maintaining adequate charging speed.
Data Source
AI summary
A display panel includes a display area and a first peripheral area located around the display area. A first gate driver is provided in the first peripheral area. The display panel is further provided with a plurality of first driving signal lines and a plurality of second driving signal lines. The plurality of first driving signal lines are arranged in a different layer from a layer in which the plurality of second driving signal lines are located. The m-th first driving signal line of the plurality of first driving signal lines and the k-th second driving signal line of the plurality of second driving signal lines are both electrically connected, in the first peripheral area, to an m-th output terminal of the first gate driver, where m is an integer greater than or equal to 1 and k is also an integer greater than or equal to 1.