Display Panel Subpixel Circuit Layout for Parasitic Capacitance Control
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Solution Overview
Problem
As display panel resolution increases, the proximity of gate electrodes and data lines leads to parasitic capacitance, causing abnormal brightness and affecting display quality due to voltage changes in the driving transistor.
Innovation Solution
The display panel design includes specific arrangements of gate and data line patterns, conductive connections, and shielding layers to prevent overlap and minimize parasitic capacitance, ensuring stable gate voltage and improved display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the display panel is increased, then the display quality is improved, but the distance between the gate electrode and data line becomes smaller, causing parasitic capacitance to increase
Solution Approach 1:
The patent extracts the harmful parasitic capacitance effect by separating the gate line pattern and data line pattern into different spatial layers. The gate line pattern is positioned in a first region while the data line pattern is positioned in a second region, with their orthographic projections on the substrate being non-overlapping. This spatial extraction eliminates the parasitic capacitance coupling between gate and data lines while maintaining high display resolution.
Solution Approach 2:
The patent resolves the contradiction by transitioning from a two-dimensional planar layout to a three-dimensional spatial arrangement. By utilizing vertical layering (different regions in the thickness direction) to separate the gate and data line patterns, the design achieves non-overlapping projections on the substrate plane while accommodating both lines within the same pixel area, thus eliminating parasitic capacitance without compromising resolution.
2Area of stationary object
If the gate electrode and data line are positioned close to each other, then the layout space is optimized, but the voltage jump of the data signal causes abnormal brightness through parasitic capacitance
Solution Approach 1:
The patent extracts the data line pattern from the immediate vicinity of the gate electrode by positioning them in different regions. The data line pattern is extracted to a second region while the gate line pattern remains in a first region, with non-overlapping orthographic projections. This extraction eliminates the parasitic capacitance coupling that would otherwise cause gate voltage instability from data signal jumps, while still optimizing layout space utilization.
Solution Approach 2:
The patent introduces an intermediate spatial separation between the gate and data lines. By positioning the gate line pattern in a first region and the data line pattern in a second region with non-overlapping projections, an effective electrical isolation (intermediary barrier) is created that prevents parasitic capacitance coupling, thereby stabilizing gate voltage while allowing compact layout.
3Area of stationary object
If the gate line pattern and data line pattern overlap in projection, then the pixel area is utilized efficiently, but parasitic capacitance increases causing display quality degradation
Solution Approach 1:
The patent extracts the overlapping projection of gate and data line patterns by assigning them to different regions. The gate line pattern is extracted to a first region and the data line pattern to a second region, ensuring their orthographic projections on the substrate do not overlap. This extraction eliminates crosstalk while maintaining efficient pixel area utilization through three-dimensional spatial arrangement.
Data Source
AI summary
The present disclosure provides a display panel and a method of manufacturing the same and a display device. In a sub-pixel driving circuit of the display panel, a gate electrode of a driving transistor is coupled to a second electrode of a second transistor through a fourth conductive connection portion, and a second electrode plate of a storage capacitor is coupled to a second electrode of a first transistor through a third conductive connection portion, a gate electrode of the first transistor and a gate electrode of the second transistor are respectively coupled to a gate line pattern in the corresponding sub-pixel area; orthographic projection of the gate line pattern on the substrate does not overlap orthographic projection of the third conductive connecting portion on the substrate, and/or does not overlap orthographic projection of the fourth conductive connection portion on the substrate.