Display Panel Transistor Layout With Fewer Photomask Steps

The patent combines the fabrication of photosensitive transistor and driver transistor into a single integrated process. The active layer pattern is formed first, then both transistors share common source/drain electrode formation steps. This merging reduces the number of separate photomask processes from multiple to fewer, simplifying the overall fabrication complexity while maintaining the functional optimization of each transistor type through selective doping and gate electrode configurations.

The patent creates a universal fabrication process where a single active layer pattern serves as the basis for both photosensitive transistor and driver transistor formation. The source/drain electrodes and insulating layers are formed using common processes that can accommodate both transistor types, making the fabrication process multi-functional rather than requiring separate specialized processes for each transistor.

The patent performs preliminary formation of the active layer pattern that defines both photosensitive transistor and driver transistor regions before proceeding to subsequent electrode formation steps. By establishing the active layer configuration early, the patent enables parallel processing of both transistor types in later stages, reducing the overall production cycle time while maintaining precise structural control through the pre-defined active layer boundaries.

The patent implements continuous fabrication processes where source/drain electrodes and insulating layers are formed in sequence without interrupting the production flow. The process continues from active layer formation through to final transistor structure completion, eliminating idle time between separate photomask processes and maintaining continuous useful action throughout the fabrication sequence.